MT9045AN Zarlink Semiconductor, Inc., MT9045AN Datasheet - Page 12

• Manufacturer Part Number: MT9045AN
• Description: Framer, Framer Circuit, T1/E1/OC3 System Synchronizer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9045
Data Sheet
Using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs
based on the three jitter transfer functions provided.
Note that the resulting jitter transfer functions for all combinations of inputs (8kHz, 1.544MHz, 2.048MHz) and
outputs (8kHz, 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz, 19.44MHz) for a given input signal
(jitter frequency and jitter amplitude) are the same.
Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than
for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input
jitter signals (e.g., 75% of the specified maximum jitter tolerance).
Frequency Accuracy
Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an
external reference, but is operating in a free running mode. For the MT9045, the Freerun accuracy is equal to
the Master Clock (OSCi) accuracy.
Holdover Accuracy
Holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an
external reference signal, but is operating using storage techniques. For the MT9045, the storage value is
determined while the device is in Normal Mode and locked to an external reference signal.
The absolute Master Clock (OSCi) accuracy of the MT9045 does not affect Holdover accuracy, but the change
in OSCi accuracy while in Holdover Mode does.
Capture Range
Also referred to as pull-in range. This is the input frequency range over which the synchronizer must be able to
±
pull into synchronization. The MT9045 capture range is equal to
230 ppm minus the accuracy of the master
clock (OSCi). For example, a 32 ppm master clock results in a capture range of 198 ppm.
The Bellcore GR-1244-CORE standard, recommends that the PLL should be able to reject references that are
±
off the nominal frequency by more than
17 ppm. The MT9045 provides two pins, PRIOOR and SECOOR, to
±
indicate whether the primary and secondary reference are within the
17 ppm of the nominal frequency. Both
references are monitored at the same time. PRIOOR and SECOOR are updated every 1.0 to 1.5 second.
The PRIOOR and SECOOR pins on the MT9045 indicate whether the Primary and Secondary references are
within +/- 17ppm of the PLL center frequency. If the Master Oscillator clock input at the OSCi pin has an
accuracy of +/-4.6ppm then the effective out of range limits of the PRIOOR and SECOOR pins will be +/-
21.6ppm.
If there are no clock transitions at the Primary and Secondary reference inputs when the MT9045 is configured
to operate with 8kHz or 19.44MHz, then the PRIOOR and SECOOR pins will provide a 50ns high pulse width
occurring once every 1.26 seconds. The duration of the pulse width is dependent on the master clock
frequency. If there are no clock transitions at the active reference pin, the MT9045 will automatically go to
Holdover Mode and indicate this condition with the Holdover pin.
Lock Range
This is the input frequency range over which the synchronizer must be able to maintain synchronization. The
lock range is equal to the capture range for the MT9045.
Phase Slope
Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with
respect to an ideal signal. The given signal is typically the output signal. The ideal signal is of constant
frequency and is nominally equal to the value of the final output signal or final input signal.
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