MT9045AN Zarlink Semiconductor, Inc., MT9045AN Datasheet - Page 7

• Manufacturer Part Number: MT9045AN
• Description: Framer, Framer Circuit, T1/E1/OC3 System Synchronizer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9045
Data Sheet
Loop Filter - the Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all four
reference frequency selections (8kHz, 1.544MHz, 2.048MHz or 19.44MHz). This filter ensures that the jitter
transfer requirements in ETS 300 011 and AT&T TR62411 are met.
Control Circuit - the Control Circuit uses status and control information from the State Machine and the Input
Impairment Circuit to set the mode of the DPLL. The three possible modes are Normal, Holdover and Freerun.
Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter,
and based on its value, generates a corresponding digital output signal. The synchronization method of the
DCO is dependent on the state of the MT9045.
In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In Holdover Mode, the DCO is free running at a frequency equal to the last (less 30ms to 60ms) frequency the
DCO was generating while in Normal Mode.
In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20MHz source.
Lock Indicator - If the PLL is in frequency lock (frequency lock means the center frequency of the PLL is
identical to the line frequency), and the input phase offset is small enough such that no phase slope limiting is
exhibited, then the lock signal will be set high. For specific Lock Indicator design recommendations see the
Applications - Lock Indicator section.
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in
Figure 5. The Output Interface Circuit uses four Tapped Delay Lines followed by a T1 Divider Circuit, an E1
Divider Circuit, and a DS2 Divider Circuit to generate the required output signals.
Four tapped delay lines are used to generate 16.384MHz, 12.352MHz, 12.624MHz and 19.44 MHz signals.
The E1 Divider Circuit uses the 16.384MHz signal to generate four clock outputs and three frame pulse outputs.
The C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight
respectively. These outputs have a nominal 50% duty cycle.
The T1 Divider Circuit uses the 12.384MHz signal
to generate the C1.5o clock by dividing the internal C12
clock by eight. This output has a nominal 50% duty cycle.
The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a
nominal 50% duty cycle.
Zarlink Semiconductor Inc.
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