MT9045AN Zarlink Semiconductor, Inc., MT9045AN Datasheet - Page 2

• Manufacturer Part Number: MT9045AN
• Description: Framer, Framer Circuit, T1/E1/OC3 System Synchronizer
• Manufacturer: Zarlink Semiconductor, Inc.

2
The MT9045 is compliant with AT&T TR62411 and Bellcore GR-1244-CORE Stratum 3, Stratum 4 Enhanced,
and Stratum 4 and ETSI ETS 300 011; and ITU-T G.813 Option 1 for 2048 kbit/s interfaces. It will meet the
jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase
change slope, holdover frequency and MTIE requirements for these specifications.
Pin Description
MT9045
23,31
Pin #
1,10,
2
3
4
5
6
SECOOR Secondary Reference Out Of Capture Range (Output). A logic high at this pin indicates
Name
TCLR
RST
SEC
PRI
V
SS
Ground. 0 Volts. (Vss pads).
Reset (Input). A logic low at this input resets the MT9045. To ensure proper operation, the
device must be reset after reference signal frequency changes and power-up. The RST pin
should be held low to a minimum of 300ns. While the RST pin is low, all frame pulses
except RST and TSP and all clock outputs except C6o, C16o and C19o are at logic high.
The RST, TSP, C6o, C16o are at logic low during reset. The C19o is free-running during
reset. Following a reset, the input reference source and output clocks and frame pulses
are phase aligned as shown in Figure 13.
TIE Circuit Reset (Input). A logic low at this input resets the Time Interval Error (TIE)
correction circuit resulting in a realignment of input phase with output phase as shown in
Figure 13. The TCLR pin should be held low for a minimum of 300ns. This pin is internally
pulled down to VSS.
that the secondary reference is off the nominal frequency by more than
Secondary Reference (Input).
(falling edge) used for synchronization. One of four possible frequencies (8kHz, 1.544MHz,
2.048MHz or 19.44MHz) may be used. The selection of the input reference is based upon the
MS1, MS2, RSEL, and PCCi control inputs.This pin is internally pulled up to V
Primary Reference (Input). See pin description for SEC. This pin is internally pulled up to
V
DD
.
SECOOR
FLOCK
LOCK
OSCo
C1.5o
TCLR
OSCi
C19o
F16o
RSP
SEC
RST
Vdd
TSP
C4o
V
C2o
PRI
Vdd
Vss
F0o
F8o
Vss
SS
IC
Figure 2 - Pin Connections
Zarlink Semiconductor Inc.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
SSOP
This is one of two (PRI & SEC) input reference sources
Description
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TMS
TCK
TRST
TDI
TDO
PRIOOR
IC
FS1
FS2
IC
RSEL
MS1
MS2
Vdd
IC
IC
NC
Vss
PCCi
HOLDOVER
Vdd
C6o
C16o
C8o
±
17 ppm.
DD
Data Sheet
.