MCS9845 MosChip Semiconductor, MCS9845 Datasheet - Page 18

• Manufacturer Part Number: MCS9845
• Description: PCI Dual UART
• Manufacturer: MosChip Semiconductor

Page 18
MCS9845
PCI Dual UART with ISA Bridge
Modem Control Register (MCR)
The Modem Control Register is an 8-bit register that
controls an interface with a modem, data set, or
peripheral device that is emulating a modem.
MCR Bit-0:
0 = Sets the nDTR output pin to high.
1 = Sets the nDTR output pin to low.
MCR Bit-1:
0 = Sets the nRTS output pin to high.
1 = Sets the nRTS output pin to low.
MCR Bit-2:
0 = Sets the nOP1 to high during loop-back mode.
1 = Sets the nOP1 to low during loop-back mode.
MCR Bit-3:
0 = Disables UART interrupts. Sets the nOP2 to high
1 = Enables UART interrupts. This bit is gated with
MCR Bit-4:
0 = Normal operation.
1 = Internal Loop-Back mode. Provides a local loop-
In the diagnostic mode, data that is transmitted is immediately
received. This allows the processor to verify transmit and
receive data paths. The receiver and transmitter interrupts
are fully operational.
also operational, but the modem control interrupt sources
are now the lower four bits of the modem control register
instead of the four modem control inputs. All interrupts are
still controlled by the interrupt enable register.
during loop-back mode.
IER Bits 0-3. Sets the nOP2 to low during loop-
back mode.
back feature for diagnostic testing. When LOOP
is set to 1, the following occurs:
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The transmitter TX pin is set to high.
The receiver RX pin is disconnected.
The output of the transmitter shift register is
looped back into the receiver shift register
input.
The four modem inputs (nCTS, nDSR nCD
and nRI) pins are disconnected.
The four modem outputs (nDTR, nRTS,
nOP1, and nOP2) pins are internally
connected to the four modem inputs. The
four modem outputs are forced to the high
levels.
The modem control interrupts are
MCR Bit-5:
0 = 16C450/550 mode.
1 = Enable hardware fl ow control (nRTS/nCTS).
nRTS becomes active (low) when the receiver is
empty or the threshold has not been reached. When
the receiver FIFO level reaches the trigger level (1,
4, 8, or 14), nRTS is de-asserted (high). nRTS is
automatically reasserted once the receiver FIFO
is empty by reading the Receive Holding Register
(RHR).
The transmitter circuitry checks nCTS before sending
the next Data Byte. When nCTS is active (low),
the transmitter sends the next Byte. To stop the
transmitter from sending the next Byte, nCTS must
be released before the middle of the last stop bit that
is currently being sent.
MCR bits 7-6:
These bits are not used (Always 0).
Hardware fl ow control is disabled.
MCR Bit-5
1
1
0
MCR Bit-1
1
0
X
Auto RTS/CTS
Auto CTS only
Flow Control
Disabled
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Rev.
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