MCS9845 MosChip Semiconductor, MCS9845 Datasheet - Page 4

• Manufacturer Part Number: MCS9845
• Description: PCI Dual UART
• Manufacturer: MosChip Semiconductor

Page 4
MCS9845
PCI Dual UART with ISA Bridge
Pin Assignments
nDEVSEL
nFRAME
AD31-29
AD28-24
AD23-16
nRESET
AD15-11
AD10-8
nTRDY
nSTOP
nLOCK
nPERR
nSERR
AD7-0
nIRDY
IDSEL
Name
CLK
PAR
126-128
34-38
40-42
46-53
11-18
122
121
Pin
2-6
23
24
25
27
28
26
29
30
31
9
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I
33 MHz PCI System Clock input.
PCI system Reset (active low).
Resets all internal registers, sequencers, and signals to a consistent state. During
reset condition, AD31-0 and nSER are tri-stated.
Multiplexed PCI Address/Data bus.
During the address phase, AD31-0 contain a physical address. Data is stable and
valid when nIRDY and nTRDY are asserted (active).
See AD31-29 description.
See AD31-29 description.
See AD31-29 description.
See AD31-29 description.
See AD31-29 description.
nFRAME is asserted by the current Bus Master to indicate the beginning of
an transfer. nFRAME remains active until the last Byte of the transfer is to be
processed.
Initiator Ready.
During a write, nIRDY asserted indicates that the initiator is driving valid data onto
the data bus. During a read, nIRDY asserted indicates that the initiator is ready to
accept data from the target device.
Target Ready (three-state).
Asserted when the target is ready to complete the current data phase.
Asserted to indicate that the target wishes the initiator to stop the transaction in
process on the current data phase.
Indicates an atomic operation that may require multiple transactions to complete.
Initialization Device Select.
Used as a chip select during confi guration read and write transactions.
Device Select (three-state).
Asserted when the target has decoded one of its addresses.
Parity Error (three-state).
Used to report parity errors during all PCI transactions except a special cycle. The
minimum duration of nPERR is one clock cycle.
System Error (open drain).
This pin goes low when address parity errors are detected.
Parity.
Even Parity is applied across AD31-0 and nC/BE3-0. PAR is stable and valid one
clock after the address phase. For the data phase, PAR is stable and valid one
clock after either nIRDY is asserted on a write transaction, or nTRDY is asserted
on a read transaction.
Description
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Rev.
2.5