MCS9845 MosChip Semiconductor, MCS9845 Datasheet - Page 14

• Manufacturer Part Number: MCS9845
• Description: PCI Dual UART
• Manufacturer: MosChip Semiconductor

Page 14
MCS9845
PCI Dual UART with ISA Bridge
UART Register Descriptions
Transmitter Holding Register (THR)
The transmitter section consists of a Transmitter
Holding Register (THR) and a Transmitter Shift
Register (TSR).
FIFO. Transmitter control is a function of the Line
Control Register (LCR). The THR receives data off
the internal data bus, and when the shift register is
idle, moves it into the TSR. The TSR serializes the
data and outputs it at TX. In the 16C450 mode, if the
THR is empty and the Transmitter Holding Register
Empty (THRE) interrupt is enabled (IER-1=1), an
interrupt is generated. This interrupt is cleared when
a character is loaded into the Transmitter Holding
Register. In the FIFO (16C550) mode, the interrupts
are generated based on the control setup in the FIFO
Control Register (FCR).
Receiver Holding Register (RHR)
The receiver section consists of a Receiver Shift
Register (RSR) and a Receiver Holding Register
(RHR). The RHR is actually a 16-Byte FIFO. Timing
for the Receiver Shift Register is supplied by the 16x-
receiver clock. Receiver control is a function of the
Line Control Register (LCR). The RSR receives serial
data from RX. The RSR then concatenates the data
and moves it into the RHR FIFO. In the 16C450 mode,
when a character is placed in the Receiver Holding
Register and the Received Data Available interrupt
is enabled (IER-0=1), an interrupt is generated. This
interrupt is cleared when the data is read out of the
Receiver Holding Register.
mode, the interrupts are generated based on the
control setup in the FIFO Control Register (FCR).
The THR is actually a 16-Byte
In the FIFO (16C550)
Interrupt Enable Register (IER)
The Interrupt Enable Register enables each of the fi ve
types of interrupts and INT pin response to an interrupt
generation. The Interrupt Enable Register can also be
used to disable the interrupt system by setting bits 0-3
to logic 0. The contents of this register are described
below:
IER Bit-0:
0 = Disables the Received Data Available interrupt.
1 = Enables the Received Data Available interrupt.
IER Bit-1:
0 = Disables the Transmitter Holding Register Empty
1 = Enables the Transmitter Holding Register Empty
IER Bit-2:
0 = Disables the Receiver Line Status interrupt.
1 = Enables the Receiver Line Status interrupt.
IER Bit-3:
0 = Disables the Modem Status interrupt.
1 = Enables the Modem Status interrupt.
IER Bits 7-4:
These bits are not used (always set to 0).
interrupt.
interrupt.
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