LTC1871 Linear Technology, LTC1871 Datasheet - Page 21

• Manufacturer Part Number: LTC1871
• Description: Wide Input Range/ No RSENSE Current Mode Boost/ Flyback and SEPIC Controller
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
5. With the input voltage to the IC bootstrapped to the
6. The diode for this design must handle a maximum DC
7. The output capacitor usually consists of a high valued
The inductor ripple current is:
And so the inductor value is:
The component chosen is a 1 H inductor made by
Sumida (part number CEP125-H 1ROMH) which has a
saturation current of greater than 20A.
output of the power supply (5V), a logic-level MOSFET
can be used. Because the duty cycle is 39%, the
maximum SENSE pin threshold voltage is reduced from
its low duty cycle typical value of 150mV to approxi-
mately 140mV. Assuming a MOSFET junction tempera-
ture of 125 C, the room temperature MOSFET R
should be less than:
The MOSFET used was the Fairchild FDS7760A, which
has a maximum R
of greater than 30V, and a gate charge of 37nC at 5V
V
output current of 10A and be rated for a minimum
reverse voltage of V
On Semiconductor (MBRB2515L) was chosen for its
high power dissipation capability.
bulk C connected in parallel with a lower valued, low
ESR ceramic. Based on a maximum output ripple
voltage of 1%, or 50mV, the bulk C needs to be greater
than:
L
GS
I
L
R
.
V
DS ON
0 140
IN MIN
.
I
(
(
L
•
•
1
)
f
I
O MAX
)
–
V
(
•
D
•
V
D
MAX
SENSE MAX
MAX
1
U
)
DS(ON)
0 4
OUT
(
1 0 39
2
0 4
.
4 6
– .
. •
U
.
, or 5V. A 25A, 15V diode from
of 8m at 4.5V V
•
A
)
1 0 39
7
3 3
•
•
– .
.
A
300
7
1
V
• .
1 5
W
kHz
2
1
–
4 6
• .
•
6 8
.
D
I
0 39 0 93
O MAX
.
MAX
A
(
m
GS
U
)
, a BV
•
.
DS(ON)
T
DSS
H
8. The choice of an input capacitor for a boost converter
PC Board Layout Checklist
1. In order to minimize switching noise and improve
The RMS ripple current rating for this capacitor needs
to exceed:
To satisfy this high RMS current demand, four 150 F
Panasonic capacitors (EEFUEOJ151R) are required.
In parallel with these bulk capacitors, two 22 F, low
ESR (X5R) Taiyo Yuden ceramic capacitors
(JMK325BJ226MM) are added for HF noise reduction.
Check the output ripple with a single oscilloscope
probe connected directly across the output capacitor
terminals, where the HF switching currents flow.
depends on the impedance of the source supply and the
amount of input ripple the converter will safely tolerate.
For this particular design and lab setup a 100 F Sanyo
Poscap (6TPC 100M), in parallel with two 22 F Taiyo
Yuden ceramic capacitors (JMK325BJ226MM) is re-
quired (the input and return lead lengths are kept to a
few inches, but the peak input current is close to 20A!).
As with the output node, check the input ripple with a
single oscilloscope probe connected across the input
capacitor terminals.
output load regulation, the GND pin of the LTC1871
should be connected directly to 1) the negative termi-
nal of the INTV
terminal of the output decoupling capacitors, 3) the
source of the power MOSFET or the bottom terminal of
the sense resistor, 4) the negative terminal of the input
capacitor and 5) at least one via to the ground plane
I
C
7
0 01 5
RMS COUT
OUT
A
. •
•
(
5
V
0 01
7
V
. •
A
3 3
•
)
I
– .
OUT MAX
.
300
CC
3 3
V
I
O MAX
decoupling capacitor, 2) the negative
(
V
kHz
(
OUT
V
)
)
•
5
•
f
A
466
V
O
V
F
–
IN MIN
V
(
IN MIN
(
)
LTC1871
)
21