LTC1871 Linear Technology, LTC1871 Datasheet - Page 23

• Manufacturer Part Number: LTC1871
• Description: Wide Input Range/ No RSENSE Current Mode Boost/ Flyback and SEPIC Controller
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
3. Place the C
4. The high di/dt loop from the bottom terminal of the
5. Check the stress on the power MOSFET by measuring
6. Place the small-signal components away from high
7. If a sense resistor is used in the source of the power
is to be used for high DC currents, choose a path away
from the small-signal components.
INTV
carries high di/dt MOSFET gate drive currents. A low
ESR and ESL 4.7 F ceramic capacitor works well here.
output capacitor, through the power MOSFET, through
the boost diode and back through the output capacitors
should be kept as tight as possible to reduce inductive
ringing. Excess inductance can cause increased stress
on the power MOSFET and increase HF noise on the
output. If low ESR ceramic capacitors are used on the
output to reduce output noise, place these capacitors
close to the boost diode in order to keep the series
inductance to a minimum.
its drain-to-source voltage directly across the device
terminals (reference the ground of a single scope probe
directly to the source pad on the PC board). Beware of
inductive ringing which can exceed the maximum speci-
fied voltage rating of the MOSFET. If this ringing cannot
be avoided and exceeds the maximum rating of the
device, either choose a higher voltage device or specify
an avalanche-rated power MOSFET. Not all MOSFETs
are created equal (some are more equal than others).
frequency switching nodes. In the layout shown in
Figure 14, all of the small-signal components have been
placed on one side of the IC and all of the power
components have been placed on the other. This also
allows the use of a pseudo-Kelvin connection for the
signal ground, where high di/dt gate driver currents
flow out of the IC ground pin in one direction (to the
bottom plate of the INTV
small-signal currents flow in the other direction.
MOSFET, minimize the capacitance between the SENSE
pin trace and any high frequency switching nodes. The
LTC1871 contains an internal leading edge blanking
time of approximately 180ns, which should be ad-
equate for most applications.
CC
and GND pins on the IC package. This capacitor
VCC
capacitor immediately adjacent to the
U
U
CC
decoupling capacitor) and
W
U
8. For optimum load regulation and true remote sensing,
9. For applications with multiple switching power con-
SEPIC Converter Applications
The LTC1871 is also well suited to SEPIC (single-ended
primary inductance converter) converter applications. The
SEPIC converter shown in Figure 16 uses two inductors.
The advantage of the SEPIC converter is the input voltage
may be higher or lower than the output voltage, and the
output is short-circuit protected.
the top of the output resistor divider should connect
independently to the top of the output capacitor (Kelvin
connection), staying away from any high dV/dt traces.
Place the divider resistors near the LTC1871 in order to
keep the high impedance FB node short.
verters connected to the same input supply, make sure
that the input filter capacitor for the LTC1871 is not
shared with other converters. AC input current from
another converter could cause substantial input voltage
ripple, and this could interfere with the operation of the
LTC1871. A few inches of PC trace or wire (L 100nH)
between the C
V
problems.
IN
V
V
V
IN
IN
IN
should be sufficient to prevent current sharing
+
+
+
Figures 16. SEPIC Topolgy and Current Flow
16b. Current Flow During Switch On-Time
16c. Current Flow During Switch Off-Time
•
•
•
L1
IN
SW
of the LTC1871 and the actual source
16a. SEPIC Topology
+
+
+
V
V
C1
IN
IN
L2
•
•
•
D1
D1
C
OUT
+
+
+
LTC1871
V
V
V
OUT
OUT
OUT
R
R
R
L
L
L
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