LTC1871 Linear Technology, LTC1871 Datasheet - Page 27

• Manufacturer Part Number: LTC1871
• Description: Wide Input Range/ No RSENSE Current Mode Boost/ Flyback and SEPIC Controller
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
and the diode junction temperature is:
The R
the R
the board to the ambient temperature in the enclosure.
SEPIC Converter: Output Capacitor Selection
Because of the improved performance of today’s electro-
lytic, tantalum and ceramic capacitors, engineers need to
consider the contributions of ESR (equivalent series resis-
tance), ESL (equivalent series inductance) and the bulk
capacitance when choosing the correct component for a
given output ripple voltage. The effects of these three
parameters (ESR, ESL, and bulk C) on the output voltage
ripple waveform are illustrated in Figure 17 for a typical
coupled-inductor SEPIC converter.
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step and the charging/discharging V.
For the purpose of simplicity we will choose 2% for the
maximum output ripple, to be divided equally between the
ESR step and the charging/discharging V. This percent-
age ripple will change, depending on the requirements of
the application, and the equations provided below can
easily be modified.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor can be determined using the
following equation:
where:
For the bulk C component, which also contributes 1% to
the total ripple:
T
ESR
I
C
D PEAK
J
OUT
(
TH(JC)
= T
TH(JA)
COUT
A
)
+ P
for the device plus the thermal resistance from
0 01
to be used in this equation normally includes
. •
I
D
O MAX
1
(
0 01
• R
I
D PEAK
. •
(
V
2
O
TH(JA)
U
)
•
V
•
f
O
)
I
O MAX
(
U
)
•
V
V
W
O
IN MIN
(
V
D
)
1
U
For many designs it is possible to choose a single capaci-
tor type that satisfies both the ESR and bulk C require-
ments for the design. In certain demanding applications,
however, the ripple voltage can be improved significantly
by connecting two or more types of capacitors in parallel.
For example, using a low ESR ceramic capacitor can
minimize the ESR step, while an electrolytic or tantalum
capacitor can be used to supply the required bulk C.
Once the output capacitor ESR and bulk capacitance have
been determined, the overall ripple voltage waveform
should be verified on a dedicated PC board (see Board
Layout section for more information on component place-
ment). Lab breadboards generally suffer from excessive
series inductance (due to inter-component wiring), and
these parasitics can make the switching waveforms look
significantly worse than they would be on a properly
designed PC board.
The output capacitor in a SEPIC regulator experiences
high RMS ripple currents, as shown in Figure 17. The RMS
output capacitor ripple current is:
Note that the ripple current ratings from capacitor manu-
facturers are often based on only 2000 hours of life. This
makes it advisable to further derate the capacitor or to
choose a capacitor rated at a higher temperature than
required. Several capacitors may also be placed in parallel
to meet size or height requirements in the design.
Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance through-
hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest product of
ESR and size of any aluminum electrolytic, at a somewhat
higher price.
In surface mount applications, multiple capacitors may
have to be placed in parallel in order to meet the ESR or
RMS current handling requirements of the application.
Aluminum electrolytic and dry tantalum capacitors are
both available in surface mount packages. In the case of
tantalum, it is critical that the capacitors have been surge
tested for use in switching power supplies. An excellent
I
RMS COUT
(
)
I
O MAX
(
)
•
V
IN MIN
V
(
O
)
LTC1871
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