LTC3826 Linear Technology, LTC3826 Datasheet - Page 8

• Manufacturer Part Number: LTC3826
• Description: 2-Phase Synchronous Step-Down Controller
• Manufacturer: Linear Technology

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PIN FUNCTIONS
LTC3826
SENSE1
Differential Current Comparators.
PLLLPF (Pin 2): The phase-locked loop’s lowpass fi lter is
tied to this pin when synchronizing to an external clock.
Alternatively, tie this pin to GND, INTV
select 250kHz, 530kHz or 390kHz switching frequency.
PHASMD (Pin 3): Control Input to Phase Selector which
determines the phase relationships between controller 1,
controller 2 and the CLKOUT signal.
CLKOUT (Pin 4): Output Clock Signal available to daisy-
chain other controller ICs for additional MOSFET driver
stages/phases.
PLLIN/MODE (Pin 5): External Synchronization Input to
Phase Detector and Forced Continuous Control Input. When
an external clock is applied to this pin, the phase-locked
loop will force the rising TG1 signal to be synchronized
with the rising edge of the external clock. In this case, an
R-C fi lter must be connected to the PLLLPF pin. When
not synchronizing to an external clock, this input, which
acts on both controllers, determines how the LTC3826
operates at light loads. Pulling this pin below 0.7V selects
Burst Mode operation. Tying this pin to INTV
continuous inductor current operation. Tying this pin to
a voltage greater than 0.9V and less than INTV
selects pulse skipping operation.
SGND (Pins 6, 33): Small Signal Ground common to both
controllers, must be routed separately from high current
grounds to the common (–) terminals of the C
tors. The Exposed Pad is SGND. It must be soldered to
PCB ground for rated thermal performance.
RUN1, RUN2 (Pins 7, 8): Digital Run Control Inputs for
Each Controller. Forcing either of these pins below 0.7V
shuts down that controller. Forcing both of these pins below
0.7V shuts down the entire LTC3826, reducing quiescent
current to approximately 4μA.
FOLDDIS (Pin 14): Foldback Current Disable Input Pin.
Driving this pin high (to INTV
limiting during short-circuit or overcurrent conditions.
8
–
, SENSE2
–
(Pins 1, 9): The (–) Input to the
CC
) disables foldback current
CC
or leave fl oating to
IN
CC
CC
capaci-
forces
–1.2V
INTV
Regulator. The driver and control circuits are powered
from this voltage source. Must be decoupled to power
ground with a minimum of 4.7μF tantalum or other low
ESR capacitor.
EXTV
Connected to INTV
bypassing the internal LDO powered from V
EXTV
the Applications Information section. Do not exceed 10V
on this pin.
PGND (Pin 21): Driver Power Ground. Connects to the
sources of bottom (synchronous) N-channel MOSFETs,
anodes of the Schottky rectifi ers and the (–) terminal(s)
of C
V
be tied between this pin and the signal ground pin.
BG1, BG2 (Pins 23, 18): High Current Gate Drives for Bot-
tom (Synchronous) N-Channel MOSFETs. Voltage swing
at these pins is from ground to INTV
BOOST1, BOOST2 (Pins 24, 17): Bootstrapped Supplies
to the Top Side Floating Drivers. Capacitors are connected
between the BOOST and SW pins and Schottky diodes are
tied between the BOOST and INTV
at the BOOST pins is from INTV
SW1, SW2 (Pins 25, 16): Switch Node Connections to
Inductors. Voltage swing at these pins is from a Schottky
diode (external) voltage drop below ground to V
TG1, TG2 (Pins 26, 15): High Current Gate Drives for
Top N-Channel MOSFETs. These are the outputs of fl oat-
ing drivers with a voltage swing equal to INTV
superimposed on the switch node voltage SW.
PGOOD1 (Pin 27): Open-Drain Logic Output. PGOOD1 is
pulled to ground when the voltage on the V
within ±10% of its set point.
IN
(Pin 22): Main Supply Pin. A bypass capacitor should
IN
CC
CC
CC
.
(Pin 19): Output of the Internal Linear Low Dropout
(Pin 20): External Power Input to an Internal LDO
is higher than 4.7V. See EXTV
CC
. This LDO supplies INTV
CC
CC
to (V
CC
pins. Voltage swing
.
CC
IN
+ INTV
Connection in
FB1
IN
CC
whenever
CC
pin is not
IN
CC
– 0.5V
power,
.
).
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