SC16C850V NXP Semiconductors, SC16C850V Datasheet - Page 14
SC16C850V
Manufacturer Part Number
SC16C850V
Description
XScale VLIO bus interface
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C850V.pdf
(47 pages)
www.DataSheet.in
NXP Semiconductors
SC16C850V_4
Product data sheet
Fig 6.
AD0 to AD7
LOWPWR
Internal Loopback mode diagram
RESET
IOW
IOR
LLA
INT
CS
SC16C850V
INTERRUPT
REGISTER
CONTROL
CONTROL
DATA BUS
CONTROL
SELECT
POWER
LOGIC
LOGIC
LOGIC
DOWN
AND
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Rev. 04 — 14 January 2008
XTAL1
GENERATOR
CLOCK AND
BAUD RATE
TRANSMIT
REGISTER
REGISTER
CONTROL
CONTROL
RECEIVE
LOGIC
LOGIC
FLOW
FLOW
FIFO
FIFO
XTAL2
TRANSMIT
REGISTER
REGISTER
RECEIVE
CONTROL
SHIFT
SHIFT
MODEM
LOGIC
ENCODER
DECODER
OP1
OP2
IR
IR
MCR[4] = 1
SC16C850V
002aac558
© NXP B.V. 2008. All rights reserved.
TX
RX
RTS
CTS
DTR
DSR
RI
CD
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