fs3862 Fortune Semiconductor Corporation, fs3862 Datasheet - Page 20

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fs3862

Manufacturer Part Number
fs3862
Description
8-bit Mcu With 1k Program Eprom, 64-byte Sram, 5-bit I/o Port, Intelligent Charger Management Controller
Manufacturer
Fortune Semiconductor Corporation
Datasheet
Rev. 1.3
The CPU has a “RST_” pin for external reset usage. When “RST_” is in logic “low” state, the CPU will go into
external reset status. The external R/C circuit for reset is shown as following. When VDD changes from “low” to
“high”, the CPU external reset status will be released, and the CPU will be in normal operating condition.
The signal from the “RST_” pin to CPU should remain in logic “low” state for more than 2µs to reset the CPU. If
the signal from the “RST_” pin to CPU is in “low” state less than 2µs, the CPU will not be reset.
9.10
Address Name Content ( u mean unknown or unchanged)
12H
13H
“1”: GPIO[N] with pull-up resistor.
9.11
GPIO[N] is the data register of I/O port.
LED[N] is the data register LED Display. can be as Source or sink LED[N] display.(10mA)
LED[N]EN =”0”: LED[N] is as input port, “1”: LED[N] is as output port.
GPIO[N]OEN =”0”: GPIO [N] is as input port, “1”: GPIO [N] is as output port.
GPIO[N]PU : I/O ports with pull-up resistor enable control. GPIO[N]PU=”0”: GPIO[N] without pull-up resistor,
GPIO[N] Internal pull up 10kΩ.
LED and General I/O
External Reset
LEDCTL
GPIO
LED1EN
-
Fig.9-2: the Minimum Reset Period to Reset the CPU
GPIO1OEN GPIO1 GPIO1PU
Fig.9-1: the Reset Circuit and the Reset Timing
LED1
LED0EN
LED0
-
GPIO2OEN
GPIO0OEN
GPIO2
GPIO0
GPIO2PU 0000u000
GPIO0PU u000u000
Reset
State
FS3862
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