fs3862 Fortune Semiconductor Corporation, fs3862 Datasheet - Page 26

• Manufacturer Part Number: fs3862
• Description: 8-bit Mcu With 1k Program Eprom, 64-byte Sram, 5-bit I/o Port, Intelligent Charger Management Controller
• Manufacturer: Fortune Semiconductor Corporation

GOTO
Syntax
Operation
Flag Affected
Description
Cycle
INCF
Syntax
Operation
Flag Affected
Description
Cycle
Example 1:
INCF OPERAND,0
Example 2:
INCF OPERAND,1
IORLW
Syntax
Operation
Flag Affected
Description
Cycle
Example:
IORLW 85H
Rev. 1.3
Unconditional Branch
GOTO k
0 ≤ k ≤ 1FFFh
PC ← k
None
The immediate address is loaded
into PC.
2
Increment f
INCF f, d
0 ≤ f ≤ FFh
d ∈ [0,1]
[Destination] ← [f] +1
Z
[f] is incremented. If d is 0, the
result is stored in the W register. If
d is 1, the result is stored back in
[f].
1
Before instruction:
After instruction:
W = 24h, OPERAND = 23h
Before instruction:
After instruction:
Inclusive OR literal with W
IORLW k
0 ≤ k ≤ FFh
[W] ← [W] | k
Z
Inclusive OR the content of the W
register and the eight-bit literal
"k". The result is stored in the W
register.
1
Before instruction:
After instruction:
W = 88h, OPERAND = 23h
W = 88h, OPERAND = 23h
W = 88h, OPERAND = 24h
W = 69h
W = EDh
HALT
Syntax
Operation
Flag Affected
Description
Cycle
INCFSZ
Syntax
Operation
Flag Affected
Description
Cycle
Example:
Node INCFSZ FLAG, 1
OP1
OP2
IORWF
Syntax
Operation
Flag Affected
Description
Cycle
Example:
IORWF OPERAND,1
:
:
Stop CPU Core Clock
HALT
CPU Stop
None
CPU clock is stopped. Oscillator
is running. CPU can be waked up
by internal and external interrupt
sources.
1
Increment f, skip if zero
INCFSZf, d
0 ≤ f ≤ FFh
d ∈ [0,1]
[Destination] ← [f] + 1, skip if the
result is zero
None
[f] is incremented. If d is 0, the
result is stored in the W register. If
d is 1, the result is stored back in
[f].
fetched instruction is discarded
and a NOP is executed instead of
making it a two-cycle instruction.
1, 2
Before instruction:
After instruction:
Inclusive OR W with f
IORWF f, d
0 ≤ f ≤ FFh
d ∈ [0,1]
[Destination] ← [W] | [f]
Z
Inclusive OR the content of the W
register and [f]. If d is 0, the result
is stored in the W register. If d is
1, the result is stored back in [f].
1
Before instruction:
After instruction:
If the result is 0, then the next
PC = address (Node)
[FLAG] = [FLAG] + 1
If [FLAG] = 0
If [FLAG] ≠ 0
W = 88h, OPERAND = 23h
W = 88h, OPERAND = ABh
PC = address(OP2)
PC = address(OP1)
FS3862
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