fs3862 Fortune Semiconductor Corporation, fs3862 Datasheet - Page 24

• Manufacturer Part Number: fs3862
• Description: 8-bit Mcu With 1k Program Eprom, 64-byte Sram, 5-bit I/o Port, Intelligent Charger Management Controller
• Manufacturer: Fortune Semiconductor Corporation

ANDLW
Syntax
Operation
Flag Affected
Description
Cycle
Example:
ANDLW 5Fh
BCF
Syntax
Operation
Flag Affected
Description
Cycle
Example:
BCF FLAG, 2
BTFSC
Syntax
Operation
Flag Affected
Description
Cycle
Example:
Node BTFSC FLAG, 2
OP1
OP2
:
:
Rev. 1.3
AND literal with W
ANDLW k
0 ≤ k ≤ FFh
[W] ← [W] AND k
Z
AND the content of the W register
with the eight-bit literal "k".
The result is stored in the W
register.
1
Before instruction:
After instruction:
Bit Clear f
BCF f, b
0 ≤ f ≤ FFh
0 ≤ b ≤ 7
[f<b>] ← 0
None
Bit b in [f] is reset to 0.
1
Before instruction:
After instruction:
Bit Test skip if Clear
BTFSC f, b
0 ≤ f ≤ FFh
0 ≤ b ≤ 7
Skip if [f<b>] = 0
None
If bit 'b' in [f] is 0, the next fetched
instruction is discarded and a
NOP is executed instead of
making it a two-cycle instruction.
1, 2
Before instruction:
After instruction:
W = A3h
W = 03h
FLAG = 8Dh
FLAG = 89h
PC = address (Node)
If FLAG<2> = 0
If FLAG<2> = 1
PC = address(OP2)
PC = address(OP1)
ANDWF
Syntax
Operation
Flag Affected
Description
Cycle
Example 1:
ANDWF OPERAND,0
Example 2:
ANDWF OPERAND,1
BSF
Syntax
Operation
Flag Affected
Description
Cycle
Example:
BSF FLAG, 2
BTFSS
Syntax
Operation
Flag Affected
Description
Cycle
Example:
Node BTFSS FLAG, 2
OP1
OP2
:
:
AND W and f
ANDWF f, d
0 ≤ f ≤ FFh
d ∈ [0,1]
[Destination] ← [W] AND [f]
Z
AND the content of the W register
with [f].
If d is 0, the result is stored in the
W register.
If d is 1, the result is stored back
in f.
1
Before instruction:
After instruction:
Before instruction:
After instruction:
Bit Set f
BSF f, b
0 ≤ f ≤ FFh
0 ≤ b ≤ 7
[f<b>] ← 1
None
Bit b in [f] is set to 1.
1
Before instruction:
After instruction:
Bit Test skip if Set
BTFSS f, b
0 ≤ f ≤ FFh
0 ≤ b ≤ 7
Skip if [f<b>] = 1
None
If bit 'b' in [f] is 1, the next fetched
instruction is discarded and a
NOP is executed instead of
making it a two-cycle instruction.
1, 2
Before instruction:
After instruction:
W = 0Fh, OPERAND = 88h
W = 08h, OPERAND = 88h
W = 0Fh, OPERAND = 88h
W = 88h, OPERAND = 08h
FLAG = 89h
FLAG = 8Dh
PC = address (Node)
If FLAG<2> = 0
If FLAG<2> = 1
PC = address(OP1)
PC = address(OP2)
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