spakdsp301vl100 Freescale Semiconductor, Inc, spakdsp301vl100 Datasheet - Page 2

• Manufacturer Part Number: spakdsp301vl100
• Description: Dsp56301 24-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Table of Contents
Chapter 1
Chapter 2
Chapter 3
Chapter 4
Chapter A
Index
Data Sheet Conventions
ii
OVERBAR
“asserted”
“deasserted”
Examples:
Note: Values for
Signals/Connections
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
Specifications
2.1
2.2
2.3
2.4
2.5
Packaging
3.1
3.2
3.3
3.4
Design Considerations
4.1
4.2
4.3
4.4
4.5
Power Consumption Benchmark
Indicates a signal that is active when pulled low (For example, the
low.)
Means that a high true (active high) signal is high or that a low true (active low) signal is low
Means that a high true (active high) signal is low or that a low true (active low) signal is high
V
Signal/Symbol
IL
,
DSP56301 Features.............................................................................................................................................iii
Target Applications.............................................................................................................................................iv
Product Documentation ......................................................................................................................................iv
Power ................................................................................................................................................................1-4
Ground ..............................................................................................................................................................1-4
Clock.................................................................................................................................................................1-5
Phase Lock Loop (PLL)....................................................................................................................................1-5
External Memory Expansion Port (Port A) ......................................................................................................1-6
Interrupt and Mode Control ..............................................................................................................................1-9
Host Interface (HI32)......................................................................................................................................1-10
Enhanced Synchronous Serial Interface 0 (ESSI0) ........................................................................................1-16
Enhanced Synchronous Serial Interface 1 (ESSI1) ........................................................................................1-18
Serial Communication Interface (SCI) ...........................................................................................................1-19
Timers .............................................................................................................................................................1-20
JTAG/OnCE Interface.....................................................................................................................................1-21
Maximum Ratings.............................................................................................................................................2-1
Absolute Maximum Ratings .............................................................................................................................2-2
Thermal Characteristics ....................................................................................................................................2-2
DC Electrical Characteristics............................................................................................................................2-2
AC Electrical Characteristics............................................................................................................................2-4
TQFP Package Description...............................................................................................................................3-2
TQFP Package Mechanical Drawing..............................................................................................................3-11
MAP-BGA Package Description ....................................................................................................................3-12
MAP-BGA Package Mechanical Drawing .....................................................................................................3-23
Thermal Design Considerations........................................................................................................................4-1
Electrical Design Considerations......................................................................................................................4-2
Power Consumption Considerations.................................................................................................................4-3
PLL Performance Issues ...................................................................................................................................4-4
Input (EXTAL) Jitter Requirements .................................................................................................................4-4
V
OL
PIN
PIN
PIN
PIN
,
V
IH
, and
V
OH
DSP56301 Technical Data, Rev. 10
are defined by individual product specifications.
True
False
True
False
Logic State
Asserted
Deasserted
Asserted
Deasserted
Signal State
RESET
Freescale Semiconductor
pin is active when
Voltage
V
V
V
V
IH
IH
IL
IL
/V
/V
/V
/V
OL
OH
OH
OL