spakdsp301vl100 Freescale Semiconductor, Inc, spakdsp301vl100 Datasheet - Page 75

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spakdsp301vl100

Manufacturer Part Number
spakdsp301vl100
Description
Dsp56301 24-bit Digital Signal Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
2.5.11 JTAG Timing
Freescale Semiconductor
Notes:
No.
500
501
502
503
504
505
506
507
508
509
510
511
512
513
TCK frequency of operation (1/(T
TCK cycle time in Crystal mode
TCK clock pulse width measured at 1.5 V
TCK rise and fall times
Boundary scan input data setup time
Boundary scan input data hold time
TCK low to output data valid
TCK low to output high impedance
TMS, TDI data setup time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO high impedance
TRST assert time
TRST setup time to TCK low
1.
2.
A[0–23]
V
All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.
CLKOUT
CC
(Output)
(Output)
(Input)
GPIO
GPIO
= 3.3 V ± 0.3 V; T
Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO
and R0 contains the address of GPIO data register.
J
= −40°C to +100 °C, C
C
× 3); maximum 22 MHz)
Characteristics
492
DSP56301 Technical Data, Rev. 10
Figure 2-45.
Table 2-25.
Valid
L
1,2
= 50 pF
494
JTAG Timing
GPIO Timing
493
491
490
100.0
AC Electrical Characteristics
Min
45.0
20.0
24.0
25.0
40.0
0.0
0.0
5.0
0.0
0.0
5.0
0.0
0.0
All frequencies
Max
22.0
40.0
40.0
44.0
44.0
3.0
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-49

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