spakdsp301vl100 Freescale Semiconductor, Inc, spakdsp301vl100 Datasheet - Page 34

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spakdsp301vl100

Manufacturer Part Number
spakdsp301vl100
Description
Dsp56301 24-bit Digital Signal Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Specifications
2-8
No.
21
22
23
24
25
26
27
Delay from WR assertion to interrupt request deassertion
for level sensitive fast interrupts
Synchronous interrupt setup time from IRQA, IRQB,
IRQC, IRQD, NMI assertion to the CLKOUT Transition 2
Synchronous interrupt delay time from the CLKOUT
Transition 2 to the first external address output valid
caused by the first instruction fetch after coming out of
Wait Processing state
Duration for IRQA assertion to recover from Stop state
Delay from IRQA assertion to fetch of first instruction
(when exiting Stop)
Duration of level sensitive IRQA assertion to ensure
interrupt service (when exiting Stop)
Interrupt Request Rate
DRAM for all WS
SRAM WS = 1
SRAM WS = 2, 3
SRAM WS ≥ 4
Minimum
Maximum
PLL is not active during Stop (PCTL Bit 17 = 0) and
Stop delay is enabled (Operating Mode Register Bit 6
= 0)
PLL is not active during Stop (PCTL Bit 17 = 0) and
Stop delay is not enabled (Operating Mode Register
Bit 6 = 1)
PLL is active during Stop (PCTL Bit 17 = 1) (Implies
No Stop Delay)
PLL is not active during Stop (PCTL Bit 17 = 0) and
Stop delay is enabled (Operating Mode Register Bit 6
= 0)
PLL is not active during Stop (PCTL Bit 17 = 0) and
Stop delay is not enabled (Operating Mode Register
Bit 6 = 1)
PLL is active during Stop (PCTL Bit 17 = 1) (implies no
Stop delay)
HI32, ESSI, SCI, Timer
DMA
IRQ, NMI (edge trigger)
IRQ, NMI (level trigger)
Table 2-7.
2, 3
Characteristics
7
1
Reset, Stop, Mode Select, and Interrupt Timing
2, 3
DSP56301 Technical Data, Rev. 10
PLC × ET
PLC × ET
PLC × ET
(WS + 3.5) × T
(WS + 3.5) × T
(WS + 2.5) × T
(WS + 3.5) × T
(WS + 3.5) × T
(WS + 2.5) × T
(WS + 3) × T
(WS + 3) × T
PLC × ET
(9.25 ± 0.5) × TC
(20.5 ± 0.5) × T
24.75 × T
8.25 × T
Expression
PLC/2) × T
PLC/2) × T
C
100 MHz:
100 MHz:
100 MHz:
100 MHz:
C
0.5) × T
C
80 MHz:
80 MHz:
80 MHz:
80 MHz:
5.5 × T
12 × T
12 × T
8 × T
8 × T
× PDF + (128 K −
× PDF + (23.75 ±
× PDF + (128K −
C
C
C
C
× PDF +
C
C
C
C
C
C
+ 1.0
C
C
C
+ 5.0
C
C
C
C
– 10.94
– 12.4
– 10.94
– 10.94
– 10.94
C
– 12.4
– 12.4
– 12.4
C
C
290.6 ns
116.6
109.4
Min
17.0
15.4
68.8
7.4
7.4
1.6
6
80 MHz
(Continued)
15.4 ms
Note 8
Note 8
Note 8
Note 8
314.4
121.9
150.0
100.0
100.0
150.0
Max
17.0
T
C
Freescale Semiconductor
232.5
Min
83.5
87.5
13.6
12.3
55.0
5.9
5.9
1.3
ns
100 MHz
Note 8
Note 8
Note 8
Note 8
252.5
120.0
120.0
Max
13.6
12.3
97.5
80.0
80.0
ms
T
C
Unit
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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