spakdsp301vl100 Freescale Semiconductor, Inc, spakdsp301vl100 Datasheet - Page 56

• Manufacturer Part Number: spakdsp301vl100
• Description: Dsp56301 24-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Specifications
2.5.5.4 Arbitration Timings
2-30
Notes:
No.
212
213
214
215
216
217
218
219
220
221
222
223
224
CLKOUT high to BR assertion/deassertion
BG asserted/deasserted to CLKOUT high
(setup)
CLKOUT high to BG deasserted/asserted
(hold)
BB deassertion to CLKOUT high (input setup)
CLKOUT high to BB assertion (input hold)
CLKOUT high to BB assertion (output)
CLKOUT high to BB deassertion (output)
BB high to BB high impedance (output)
CLKOUT high to address and controls active
CLKOUT high to address and controls high
impedance
CLKOUT high to AA active
CLKOUT high to AA deassertion
CLKOUT high to AA high impedance
1.
2.
3.
Synchronous Bus Arbitration is not recommended. Use Asynchronous mode whenever possible.
An expression is used to compute the maximum or minimum value listed, as appropriate. For timing 223, the minimum is an
absolute value.
T212 is valid for Address Trace mode when the ATE bit in the Operating Mode Register is set. BR is deasserted for internal
accesses and asserted for external accesses.
Characteristics
Table 2-16.
DSP56301 Technical Data, Rev. 10
3
maximum: 0.25 × T
Arbitration Bus Timings
Expression
0.25 × T
0.75 × T
0.25 × T
0.75 × T
C
C
C
C
2
C
+ 4.0
1
.
Min
1.0
5.0
0.0
5.0
0.0
1.0
1.0
3.1
3.1
4.1
—
—
—
80 MHz
Max
4.5
4.5
4.5
5.6
9.4
7.1
9.4
—
—
—
—
—
—
Freescale Semiconductor
Min
0.0
4.0
0.0
4.0
0.0
0.0
0.0
2.5
2.5
2.0
—
—
—
100 MHz
Max
4.0
4.0
4.0
4.5
7.5
6.5
7.5
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns