ds26518 Maxim Integrated Products, Inc., ds26518 Datasheet - Page 120

• Manufacturer Part Number: ds26518
• Description: 8-port T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Register Name
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 5: General-Purpose I/O Pins Select (GPSEL[3:1])
Table 10-11. Output Status Control
Bit 3: DS26528 Mode (528MD)
Bit 2: Ganged IBO Enable (GIBO). This bit is used to select either the internal mux for IBO operation or an
external “wire-OR” operation. Normally this bit should be set = 0 and the internal mux used.
Note: Setting GIBO disables the internal IBO mux.
configuration.
Bit 1: Global Counter Latch Enable (GCLE). A low-to-high transition on this bit will, when enabled, latch the
framer performance monitor counters. Each framer can be independently enabled to accept this input. This bit must
be cleared and set again to perform another counter latch.
Bit 0: Global Interrupt Pin Inhibit (GIPI)
GPSEL[3:1]
TSYNC/TSSYNCIO[8:1]
Normal Operation
(Tie low—unused)
000
001
010
011
100
101
110
111
0 = Normal operation.
1 = Pin definitions switch to DS26528 pins to obtain pin compatibility with the DS26528.
RSYSCLK[8:2]
0 = Use internal IBO mux.
1 = Externally “wire-OR” TSERn and RSERn for IBO operation.
0 = Normal Operation. Interrupt pin (INTB) will toggle low on an unmasked interrupt condition.
1 = Interrupt Inhibit. Interrupt pin (INTB) is forced high (inactive) when this bit is set.
TSYSCLK[8:2]
RSYSCLK1
TSYSCLK1
SPI_SEL
CLKO
GPSEL3
7
0
RLF/LTC[8:1]
GTCR1
Global Transceiver Control Register 1
00F0h
Reserved
Reserved
GPSEL2
RLF
LTC
RLF
LTC
RLF
LTC
6
0
GPSEL1
AL/RSIGF/FLOS[8:2]
5
0
AL/RSIGF/FLOS1
AL/RSIGF/FLOS[8:1]
RLF/LTC[8:2]
TSYNC[8:1]
RSYSCLK1
TSYSCLK1
TSSYNCIO
RLF/LTC1
528MD
Reserved
Reserved
RSIGF
RSIGF
FLOS
FLOS
120 of 286
AL
AL
—
4
0
GFCR1
must be set to inform the framers of the IBO
528MD
3
0
DS26518 8-Port T1/E1/J1 Transceiver
GIBO
0
2
GCLE
1
0
GIPI
0
0