ds26518 Maxim Integrated Products, Inc., ds26518 Datasheet - Page 189

• Manufacturer Part Number: ds26518
• Description: 8-port T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Bits 7 to 0: Gapped Clock Channel Select Bits for Receive Channels 1 to 32(CH[1:32])
* Note that RGCCS4 has two functions:
Register Name:
Register Description:
Register Address:
Bit #
Name
Bits 7 to 0: Receive Channels 1 to 32 Code Insertion Control Bits (CH[1:32])
0 = No clock is present on RCHCLKn during this channel time.
1 = Force a clock on RCHCLKn during this channel time. The clock will be synchronous with RCLKn if the
elastic store is disabled, and synchronous with RSYSCLKn if the elastic store is enabled.
When 2.048MHz backplane mode is selected, this register allows the user to enable the gapped clock on
RCHCLKn for any of the 32 possible backplane channels.
When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not a clock is
generated on RCHCLKn during the F-bit time:
In this mode RGCCS4.1 to RGCCS4.7 should be set to 0.
0 = Do not insert data from the Idle Code Array into the receive data stream.
1 = Insert data from the Idle Code Array into the receive data stream.
(MSB)
CH16
CH24
CH32
CH8
(MSB)
CH16
CH24
CH32
CH8
7
7
RGCCS4.0 = 0, do not generate a clock during the F-bit.
RGCCS4.0 = 1, generate a clock during the F-bit.
CH15
CH23
CH31
CH7
6
CH15
CH23
CH31
CH7
RGCCS1, RGCCS2, RGCCS3, RGCCS4
Receive Gapped Clock Channel Select Registers 1 to 4
0CCh, 0CDh, 0CEh, 0CFh + (200h x (n - 1)) : where n = 1 to 8
RCICE1, RCICE2, RCICE3, RCICE4
Receive Channel Idle Code Enable Registers 1 to 4
0D0h, 0D1h, 0D2h, 0D3h + (200h x (n - 1)) : where n = 1 to 8
6
CH14
CH22
CH30
CH6
5
CH14
CH22
CH30
CH6
5
CH13
CH21
CH29
CH5
4
CH13
CH21
CH29
CH5
4
CH12
CH20
CH28
CH4
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3
CH12
CH20
CH28
CH4
3
CH11
CH19
CH27
CH3
2
CH11
CH19
CH27
CH3
2
CH10
CH18
CH26
CH2
1
DS26518 8-Port T1/E1/J1 Transceiver
CH10
CH18
CH26
CH2
1
(F-bit)
(LSB)
CH17
CH25
CH1
CH9
0
(LSB)
CH17
CH25
CH1
CH9
RGCCS1
RGCCS2
RGCCS3
RGCCS4 (E1
Mode Only)*
0
RCICE1
RCICE2
RCICE3
RCICE4 (E1
Mode Only)