74LV74PW,118 NXP Semiconductors, 74LV74PW,118 Datasheet - Page 3

• Manufacturer Part Number: 74LV74PW,118
• Description: IC DUAL D FF POSEDG TRIG 14TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVr
• Type: D-Typer

Specifications of 74LV74PW,118

• Output Type: Differential
• Package / Case: 14-TSSOP
• Function: Set(Preset) and Reset
• Number Of Elements: 2
• Number Of Bits Per Element: 1
• Frequency - Clock: 56MHz
• Trigger Type: Positive Edge
• Current - Output High, Low: 12mA, 12mA
• Voltage - Supply: 1 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Logic Family: LV
• Logic Type: D-Type Edge Triggered Flip-Flop
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 11 ns at 3.3 V
• High Level Output Current: - 12 mA
• Low Level Output Current: 12 mA
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 1 V
• Delay Time - Propagation: -
• Technology: CMOS
• Number Of Bits: 2
• Number Of Elements: 2
• Clock-edge Trigger Type: Positive-Edge
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSSOP
• Frequency (max): 56MHz
• Operating Supply Voltage (min): 1V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time - Propagation: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 74LV74PW-T; 74LV74PW-T; 935175140118

NXP Semiconductors
5. Pinning information
74LV74_3
Product data sheet
Fig 3. Logic diagram (one flip-flop)
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14
RD
SD
CP
D
GND
1RD
1CP
1SD
1D
1Q
1Q
5.1 Pinning
1
2
3
4
5
6
7
74
001aad106
C
C
C
C
14
13
12
11
10
9
8
V
2RD
2D
2CP
2SD
2Q
2Q
CC
C
C
Rev. 03 — 28 September 2007
Dual D-type flip-flop with set and reset; positive edge-trigger
Fig 5. Pin configuration DHVQFN14
(1) The die substrate is attached to this pad using
C
C
conductive die attach material. It can not be used as
a supply pin or input.
index area
terminal 1
1CP
1SD
C
C
1Q
1Q
1D
Transparent top view
2
3
4
5
6
mna421
V CC (1)
74
13
12
11
10
9
© NXP B.V. 2007. All rights reserved.
2RD
2D
2CP
2SD
2Q
74LV74
Q
Q
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