si5338b Silicon Laboratories, si5338b Datasheet - Page 13

• Manufacturer Part Number: si5338b
• Description: I2c-programmable Any-rate , Any-output Quad Clock Generator
• Manufacturer: Silicon Laboratories

2. Functional Description
2.1. Overview
The Si5338 is a high performance, low jitter clock
generator capable of synthesizing any frequency
ranging from 0.16 to 350 MHz on each of the device's
four differential output clocks. The device accepts an
external crystal from 8 to 30 MHz or an input clock
ranging
independently user-programmable to any frequency up
to 350 MHz and select frequencies to 700 MHz. Each
differential output clock can optionally be configured to
produce
frequency, so a total of eight clock outputs at four
unique frequencies are available.
The Si5338 fractional-N PLL, comprised of a phase
detector, charge pump, loop filter, VCO, and dividers, is
fully integrated on chip to simplify design. Using Silicon
Laboratories' patented MultiSynth technology, each
output clock is generated with < 2 ps rms phase jitter
and zero ppm frequency error. The device has four
MultiSynth output dividers to provide non-integer
frequency synthesis on every differential output clock.
The Si5338 output driver is highly flexible. The signal
format of each differential output clock can be user-
specified to support LVPECL, LVDS, HCSL, CMOS,
HSTL, or SSTL. If a single-ended format is selected,
two in-phase outputs are generated per differential
buffer. In addition, each differential output clock is
supplied with an independent supply voltage ranging
from 1.4 to 3.63 V such that the device can be used in
mixed supply applications without the need for external
level translators. When an output clock is configured to
be a CMOS format, the slew rate can be user-
programmed. This slew rate control can be used to
minimize EMI on a per output clock basis.
from
INTR
two
SDA
SCL
IN4
IN1
IN2
IN3
IN5
IN6
single-ended
5
I2C_LSB/PDEC/FDEC
FDBKB
to
FDBK
OEB/PINC/FINC
700 MHz.
Osc
CLKIN
clocks
Control
Each
Figure 4. Si5338 Block Diagram
÷P1
÷P2
at
NVM
the
output
Frequency
Detector
Phase
same
Rev. 0.3
is
MultiSynth
÷N
The ability to invert output clocks is supported
regardless of the format.
The Si5338 supports an optional zero delay buffer mode
(ZDB) of operation. In this mode, one of the device
output clocks is fed back to the FDBK/FDBKB clock
input pins to implement the PLL feedback path and
nullify the phase difference between the reference input
and the output clocks.
The Si5338 has a digitally controlled phase increment/
decrement feature that allows the user to adjust the
phase of each output clock in relation to the other output
clocks. The phase of each differential output clock can
be set to an accuracy of 20 ps over a range of ±45 ns.
This feature is available over the 0.16 to 350 MHz
frequency range. Register control of this feature is
available via the microprocessor interface. This feature
is also available via pin control in some Si5338 variants
as listed in Table 10.
The
increment/decrement feature that allows the user to
dynamically transition from one frequency to another in
a programmable number of steps. This feature is
available over the 0.16 to 350 MHz frequency range.
The frequency transition is continuous and glitchless.
This feature is useful in applications that require a
continuous, variable clock frequency. It can also be
used in frequency margining applications to margin test
system
manufacturing test applications. Register control of this
feature is available via the microprocessor interface.
This feature is also available via pin control in some
Si5338 variants as listed in Table 10.
Loop
Filter
Si5338
VCO
clocks
has
MultiSynth
MultiSynth
MultiSynth
MultiSynth
during
÷M3
÷M0
÷M1
÷M2
a
digitally-controlled
design/verification/test
÷
÷
÷
÷
R1
R2
R3
R0
VDDO0
CLK0A
Si5338
CLK0B
VDDO1
CLK1A
CLK1B
VDDO2
CLK2A
CLK2B
VDDO3
CLK3A
CLK3B
frequency
13
or