si5338b Silicon Laboratories, si5338b Datasheet - Page 16

• Manufacturer Part Number: si5338b
• Description: I2c-programmable Any-rate , Any-output Quad Clock Generator
• Manufacturer: Silicon Laboratories

Si5338
2.5. Breakthrough MultiSynth
Next-generation timing architectures require a wide
range of frequencies which are often non-integer
related. Traditional clock architectures address this by
using multiple single PLL ICs, often at the expense of
BOM complexity and power. The Si5334 and Si5338
use patented MultiSynth technology to dramatically
simplify
frequency synthesis capability of 4 Phase-Locked
Loops (PLLs) in a single device, greatly minimizing size
and power requirements versus traditional solutions.
Based on a fractional-N PLL, the heart of the
architecture is a low phase noise, high frequency VCO.
The VCO supplies a high frequency output clock to the
MultiSynth block on each of the four independent output
paths. Each MultiSynth operates as a high speed
fractional divider with Silicon Laboratories' proprietary
phase error correction to divide down the VCO clock to
the required output frequency with very low jitter.
The first stage of the MultiSynth architecture is a
fractional-N divider which switches seamlessly between
the two closest integer divider values to produce the
exact output clock frequency with 0 ppm error. To
eliminate phase error generated by this process,
MultiSynth calculates the relative phase difference
2.6. Output Driver
There are four clock output channels on the Si5338
(CLK0,CLK1,CLK2,CLK3) with two signal outputs per
channel. Each channel may be programmed to be a
differential driver or a dual single ended driver. If a
channel is programmed to be single ended, then the two
outputs will default to being in phase however either
output can be inverted or turned off. A differential
channel output can have both outputs inverted together
16
Technology
timing
architectures
f
VCO
Figure 5. Silicon Labs' MultiSynth Technology
Divider Select
(DIV1, DIV2)
Fractional-N
by
Divider
integrating
MultiSynth
the
Rev. 0.3
Phase Error
Calculator
between the clock produced by the fractional-N divider
and the desired output clock and dynamically adjusts
the phase to match the ideal clock waveform. This novel
approach makes it possible to generate any output
clock frequency without sacrificing jitter performance.
Based on this architecture, the output of each
MultiSynth can produce any frequency from 5 to
fvco/8 MHz. Since the maximum VCO frequency is
2.8 MHz, the maximum frequency at the output of the
MultiSynth is 350 MHz. To support higher frequency
operation, the MultiSynth divider can be bypassed. In
bypass mode integer divide ratios of 4 and 6 are
supported, which allows for output frequencies of fvco/4
and fvco/6 MHz which translates to 367–466 MHz and
550-700 MHz respectively. Because each MultiSynth
uses the same VCO output there can be output
frequency limitations due to the frequency plan. If a
frequency of 375 MHz is needed, the VCO would need
to be at 2.25 GHz and the MultiSynth must be bypassed
to achieve an output frequency > 350 MHz. Since the
VCO frequency is 2.25 GHz, that means that all the
other CLKn outputs can have a maximum frequency of
FVCO/8 or 281.25 MHz. The Si5338 Programmer
software takes all of this, and more, into consideration in
order to allow frequency plans to be quickly and easily
synthesized.
or turned off. Si5338 output drivers can be configured
as single ended CMOS, SSTL, HSTL or differential
LVPECL, LVDS, and HCSL formats. The CMOS output
driver also has programmable rise/fall time from ~1ns to
~4 ns.
available which does not require the typical low value
resistor for DC bias.
The supply voltage requirement for each driver format
should also be set using the Si5338 programmer
A special low power LVPECL driver format is
Adjust
Phase
f
OUT