si5338b Silicon Laboratories, si5338b Datasheet - Page 14

• Manufacturer Part Number: si5338b
• Description: I2c-programmable Any-rate , Any-output Quad Clock Generator
• Manufacturer: Silicon Laboratories

Si5338
For noise reduction, the Si5338 supports spread
spectrum clocking (SSC). Down spread of –0.5% is
available
specifications. Spread spectrum is available on all
output clocks and can be individually turned on/off for
each differential output clock via the I
feature is available when the output clocks are
configured for 100 MHz operation.
The device is programmable via an I
compatible interface. The device has a maskable
interrupt output alarm pin which can be monitored for
PLL loss of lock, input clock loss of signal, and feedback
clock loss of signal conditions. The Si5338 may be
operated from a 1.8, 2.5, or 3.3 V core supply. All device
specifications are guaranteed across these three core
supply voltages. Packaged in a ROHS-6, Pb-free
4 x 4 mm QFN package, the device supports the
industrial temperature range of –40 to +85 °C.
After a power-on reset, the Si5338 reads the contents of
its non-volatile memory (NVM) and begins operation
using these parameters. By default, the Si5338 NVM is
blank and the device must be written via the I
interface before the PLL acquires lock and generates
output clocks. Optionally, the default operating condition
can be user-specified and either factory-programmed or
field-programmed into the device NVM. This feature is
one-time programmable. In this mode, no user
intervention is required before the device begins
operation at the start-up configuration. A wide range of
input clock frequency, output clock frequencies, and
output clock signal formats is supported in this mode of
operation.
2.2. Si5338 Configuration Software and
Silicon Labs offers Si5338 configuration software to
simplify frequency planning and device programming.
Simply specify the desired input and output frequencies
and the software automatically calculates the VCO
frequency and PLL divider combination that yields the
lowest jitter and lowest power. This software is available
for
software is also available with the device evaluation
board, Si5338-EVB and the device programmer,
Si5338-PROG-EVB.
The Si5338-EVB is the standard evaluation board for
the device and includes an Si5338 device soldered
down
programming kit includes a socketed board and five
blank Si5338 devices which can be field-programmed
by the user to specify different start-up configurations.
Upon a subsequent power-on reset, the device will
come up in the field-programmed configuration. Contact
14
download
Programmer's Kit
on
in
the
compliance
from
board.
www.silabs.com/timing.
The
with
PCI
Si5338-PROG-EVB
2
C interface. This
Express
2
C/SMBus
This
2.0
2
Rev. 0.3
C
your local Silicon Labs sales representative for further
details regarding a Si5338 I
generator with a factory-programmed default operating
configuration.
The Si5338 software and the programming kit may also
be used to generate custom Si5334 pin-controlled clock
generators. Consult the Si5338-PROG-EVB data sheet
or the Si5334 data sheet for further details. The Si5338
is always programmable in-circuit via the I
The remainder of the functional description contains
details only needed when the Si5338 configuration
software is not used to program the device.
2.3. Crystal/Input Clock
The device can be driven from either a low frequency
fundamental mode crystal (8–30 MHz) or an external
reference clock (5–700 MHz). The crystal is connected
across pins IN1 and IN2.
The PCB traces between the crystal and the device
must be kept very short to minimize stray capacitance.
To ensure maximum compatibility with crystals from
multiple vendors, the internal crystal oscillator provides
adaptive crystal drive strength based upon the crystal
frequency. This feature provides interoperability with
any 8–30 MHz crystals with equivalent series resistance
(ESR) values ranging from 30 to 80 .
The crystal load capacitors are placed on-chip to reduce
external component count. If a crystal with a load
capacitance outside the range specified in Table 3 is
supplied to the device, it will result in a slight ppm error
in the device clock output frequencies. The Si5338
configuration software calculates the ppm error for each
output clock based on the crystal load capacitance and
can be used to null this ppm error if so desired. Consult
the Si5338 configuration software for more details.
If a reference clock is used, the device accepts a single-
ended input reference from a CMOS, HSTL, or SSTL
source on IN3 or a differential LVPECL, LVDS, or HCSL
source on IN1 and IN2. The input at IN3 is internally AC
coupled and will tolerate 3.63 V regardless of the core
VDD supply voltage. The signal applied at IN3 should
be dc-coupled. If a differential input clock is input a
100  resistor should be located very close to the
device and between IN1 and IN2. The differential signal
must be AC coupled to IN1 and IN2.
The Si5338 can operate as a clock generator or a zero
delay buffer. By default the device is configured for
clock generator mode. If zero delay buffer mode is
used, one of the device output clocks is routed to the
feedback clock input pins. The feedback clock can be
single-ended (CMOS, HSTL, or SSTL) or differential
(LVPECL, LVDS, or HCSL). The signal format of the
2
C-programmable clock
2
C interface.