si5338b Silicon Laboratories, si5338b Datasheet - Page 21

• Manufacturer Part Number: si5338b
• Description: I2c-programmable Any-rate , Any-output Quad Clock Generator
• Manufacturer: Silicon Laboratories

2.15. Self-Calibration
The device performs an internal self-calibration before
operation to optimize loop parameters and jitter
performance.
performed, the device VCO is being internally controlled
by the self-calibration state machine and the LOL alarm
is masked. The output clocks appear after the device
finishes self calibration.
2.17. Register Descriptions
See the Si5338 Register Map file for a full description of
the device registers.
2.18. I
The Si5338 control interface is a 2-wire bus for
bidirectional communication. The bus consists of a
bidirectional serial data line (SDA) and a serial clock
input (SCL). The device operates as a slave device on
the 2-wire bus and is compatible with I
Both lines must be connected to the positive supply via
an external pull-up. Standard-Mode (100 kbps) and
Fast-Mode (400 kbps) and Fast Mode+ (1000 kbps)
operation and 7-bit addressing are supported as
specified in the I
accommodate multiple Si5338 devices on the same I
bus, the Si5338A/B/C has pin 4 as I2C_LSB.
2
C Interface
While
2
C-Bus Specification standard. To
Configure Device
Powerup device
Outputs/ Reset
the
Disable Clock
via Registers
MultiSynths
Soft Reset
self-calibration
Figure 7. Si5338 Programming Sequence
2
C specifications.
DRVn_PDN = 1
MSYNTH_RESET = 1
Configure device using FlexClock software, then set:
MSYNTH_RESET = 0
DRVn_PDN = 0
SOFT_RESET = 1
is
being
2
Rev. 0.3
C
The following events will trigger a self-calibration by
default.




2.16. Device Programming
Figure 7 shows the sequence of steps that must be
used after a power-on reset to ensure proper device
operation.
The complete bus address for the device is as follows:
0111 000[I2C_LSB].
See Figure 1 and Figure 2 for the command format for
both read and write access. Data is always sent MSB
first. Table 9 includes the AC and DC electrical
parameters for the SCL and SDA I/Os, respectively. The
timing specifications and timing diagram for the I
can be found in the I
to the following URL:
http://www.nxp.com/acrobat_download/usermanuals/
UM10204_3.pdf. SDA timeout support is supported for
compatibility with SMBus interfaces. The I
3.3 V tolerant.
The I
3.63 V and should have a pullup resistor of no larger
than 1 k. When the I
below 2.25 V, the input threshold of pin 19 must be
changed by writing register 27[7] = 1.
Power on reset (POR_RESET)
Soft reset (SOFT_RESET)
Loss of signal (LOS)
Loss of lock (LOL)
2
C bus can be operated at a bus voltage of 1.71 to
2
C-Bus Specification standard. Go
2
C bus is operated at a voltage
Si5338
2
C interface is
2
C bus
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