isl12022m Intersil Corporation, isl12022m Datasheet - Page 11

• Manufacturer Part Number: isl12022m
• Description: Real Time Clock With Embedded Crystal, ??5ppm Accuracy
• Manufacturer: Intersil Corporation

ADDR. SECTION
Oscillator Compensation
The ISL12022M provides both initial timing correction and
temperature correction due to variation of the crystal
oscillator. Analog and digital trimming control is provided for
initial adjustment, and a temperature compensation function
is provided to automatically correct for temperature drift of
the crystal. Initial values for the initial AT and DT settings
(ITR0), temperature coefficient (ALPHA), crystal capacitance
(BETA), as well as the crystal turn-over temperature (XTO),
are preset internally and recalled to RAM registers on
power-up. These values can be overwritten by the user
although this is not suggested as the resulting
temperature compensation performance will be
compromised. The compensation function can be
enabled/disabled at any time and can be used in battery
mode as well.
Register Descriptions
The battery-backed registers are accessible following a
slave byte of “1101111x” and reads or writes to addresses
[00h:13h]. The defined addresses and default values are
described in Table 1. The battery backed general purpose
SRAM has a different slave address (1010111x), so it is not
possible to read/write that section of memory while
accessing the registers.
REGISTER ACCESS
The contents of the registers can be modified by performing
a byte or a page write operation directly to any register
address.
The registers are divided into 8 sections. They are:
1. Real Time Clock (7 bytes): Address 00h to 06h.
2. Control and Status (9 bytes): Address 07h to 0Fh.
00h
01h
02h
03h
04h
05h
06h
RTC
NAME
REG
MO
DW
SC
MN
HR
YR
DT
TABLE 1. REGISTER MEMORY MAP (YELLOW SHADING INDICATES READ-ONLY BITS)
11
YR23
MIL
0
0
0
0
0
7
MN22
SC22
YR22
6
0
0
0
0
SC21
MN21
HR21
YR21
DT21
5
0
0
ISL12022M
MN20
MO20
SC20
HR20
YR20
DT20
4
0
BIT
10. Crystal ALPHA at high temperature, ALPHA_H (1 byte):
11. Scratch Pad (2 bytes): Address 2Eh and 2Fh
Write capability is allowable into the RTC registers (00h to
06h) only when the WRTC bit (bit 6 of address 08h) is set to
“1”. A multi-byte read or write operation is limited to one
section per operation. Access to another section requires a
new operation. A read or write can begin at any address
within the section.
A register can be read by performing a random read at any
address at any time. This returns the contents of that register
location. Additional registers are read by performing a
sequential read. For the RTC and Alarm registers, the read
instruction latches all clock registers into a buffer, so an
update of the clock does not change the time being read. At
the end of a read, the master supplies a stop condition to
end the operation and free the bus. After a read, the address
remains at the previous address +1 so the user can execute
a current address read and continue reading the next
register.
It is not necessary to set the WRTC bit prior to writing into
the control and status, alarm, and user SRAM registers.
3. Alarm (6 bytes): Address 10h to 15h.
4. Time Stamp for Battery Status (5 bytes): Address 16h to
5. Time Stamp for V
6. Day Light Saving Time (8 bytes): 20h to 27h.
7. TEMP (2 bytes): 28h to 29h.
8. Crystal Net PPM Correction, NPPM (2 bytes): 2Ah, 2Bh
9. Crystal Turnover Temperature, XT0 (1 byte): 2Ch
MN13
MO13
SC13
HR13
DT13
YR13
3
0
1Ah.
1Fh.
2Dh
MN12
MO12
SC12
HR12
DT12
YR12
DW2
2
DD
MN11
MO11
SC11
HR11
YR11
DT11
DW1
1
Status (5 bytes): Address 1Bh to
MN10
HR10
MO10
SC10
DT10
YR10
DW0
0
RANGE
0 to 59
0 to 59
0 to 23
1 to 31
1 to 12
0 to 99
0 to 6
December 18, 2008
DEFAULT
FN6668.4
00h
00h
00h
01h
01h
00h
00h