isl12022m Intersil Corporation, isl12022m Datasheet - Page 19

• Manufacturer Part Number: isl12022m
• Description: Real Time Clock With Embedded Crystal, ??5ppm Accuracy
• Manufacturer: Intersil Corporation

alarm register, multiple registers, or all registers can be
enabled for a match.
There are two alarm operation modes: Single Event and
periodic Interrupt Mode:
• Single Event Mode is enabled by setting the bit 7 on any
• Interrupt Mode is enabled by setting the bit 7 on any of
To clear a single event alarm, the ALM bit in the status
register must be set to “0” with a write. Note that if the ARST
bit is set to 1 (address 08h, bit 7), the ALM bit will
automatically be cleared when the status register is read.
Following are examples of both Single Event and periodic
Interrupt Mode alarms.
Example 1
• Alarm set with single interrupt (IM = ”0”)
• A single alarm will occur on January 1 at 11:30 a.m.
• Set Alarm registers as follows:
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30 a.m. on January 1 (after
seconds changes from 59 to 00) by setting the ALM bit in the
status register to “1” and also bringing the IRQ/F
low.
REGISTER
ALARM
of the Alarm registers (ESCA0... EDWA0) to “1”, the IM bit
to “0”, and disabling the frequency output. This mode
permits a one-time match between the Alarm registers
and the RTC registers. Once this match occurs, the ALM
bit is set to “1” and the IRQ/F
and will remain low until the ALM bit is reset. This can be
done manually or by using the auto-reset feature.
the Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to
“1”, and disabling the frequency output. The IRQ/F
output will now be pulsed each time an alarm occurs. This
means that once the interrupt mode alarm is set, it will
continue to alarm for each occurring match of the alarm
and present time. This mode is convenient for hourly or
daily hardware interrupts in microcontroller applications
such as security cameras or utility meter reading.
MOA0
DWA0
MNA0
HRA0
SCA0
DTA0
7 6 5 4 3 2 1 0 HEX
0 0 0 0 0 0 0 0
1 0 1 1 0 0 0 0
1 0 0 1 0 0 0 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
BIT
19
OUT
output will be pulled low
B0h Minutes set to 30,
00h Seconds disabled
91h Hours set to 11,
81h Date set to 1,
81h Month set to 1,
00h Day of week
enabled
enabled
enabled
enabled
disabled
DESCRIPTION
OUT
output
OUT
ISL12022M
Example 2
• Pulsed interrupt once per minute (IM = ”1”)
• Interrupts at one minute intervals when the seconds
• Set Alarm registers as follows:
Once the registers are set, the following waveform will be
seen at IRQ/F
Note that the status register ALM bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
Time Stamp V
The TSV2B Register bytes are identical to the RTC register
bytes, except they do not extend beyond the Month. The Time
Stamp captures the FIRST V
time, and will not update upon subsequent events until cleared
(only the first event is captured before clearing). Set CLRTS = 1
to clear this register (Add 09h, PWR_V
Note that the time stamp registers are cleared to all “0”,
including the month and day, which is different from the RTC
and alarm registers (those registers default to 01h). This is
the indicator that no time stamping has occurred since the
last clear or initial power-up. Once a time stamp occurs,
there will be a non-zero time stamp.
Time Stamp Battery to V
The Time Stamp Battery to V
the RTC register bytes, except they do not extend beyond
Month. The Time Stamp captures the LAST transition of V
to V
events is retained). Set CLRTS = 1 to clear this register (Add
09h, PWR_V
REGISTER
register is at 30 seconds.
ALARM
DWA0
MNA0
MOA0
SCA0
HRA0
DTA0
DD
(only the last event of a series of power-up/power-down
RTC AND ALARM REGISTERS ARE BOTH “30s”
7 6 5 4 3 2 1 0 HEX
1 0 1 1 0 0 0 0 B0h Seconds set to 30,
0 0 0 0 0 0 0 0 00h Minutes disabled
0 0 0 0 0 0 0 0 00h Hours disabled
0 0 0 0 0 0 0 0 00h Date disabled
0 0 0 0 0 0 0 0 00h Month disabled
0 0 0 0 0 0 0 0 00h Day of week disabled
DD
FIGURE 14. IRQ/F
OUT
register).
DD
:
to Battery Registers (TSV2B)
BIT
DD
DD
60s
DD
OUT
to Battery Voltage transition
Register bytes are identical to
Registers (TSB2V)
WAVEFORM
DD
enabled
register).
DESCRIPTION
December 18, 2008
FN6668.4
BAT