isl12022m Intersil Corporation, isl12022m Datasheet - Page 14

• Manufacturer Part Number: isl12022m
• Description: Real Time Clock With Embedded Crystal, ??5ppm Accuracy
• Manufacturer: Intersil Corporation

LOW V
This bit indicates when V
pre-selected trip level (Brownout Mode). The trip points for
brownout levels are selected by three bits: V
V
LOW BATTERY INDICATOR 85% BIT (LBAT85)
This bit indicates when the battery level has dropped below
the pre-selected trip levels (85% of battery voltage). The trip
points are selected by three bits: VB85Tp2, VB85Tp1 and
VB85Tp0 in the PWR_VBAT registers.
LOW BATTERY INDICATOR 75% BIT (LBAT75)
This bit indicates when the battery level has dropped below
the pre-selected trip levels (75% of battery voltage). The trip
points are selected by three bits: VB75Tp2, VB75Tp1 and
VB75Tp0 in the PWR_VBAT registers.
REAL TIME CLOCK FAIL BIT (RTCF)
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (ISL12022M internally) when
the device powers up after having lost all power (defined as
V
whether V
the supplies does not set the RTCF bit to “1”. The first valid
write to the RTC section after a complete power failure
resets the RTCF bit to “0” (writing one byte is sufficient).
Interrupt Control Register (INT)
AUTOMATIC RESET BIT (ARST)
This bit enables/disables the automatic reset of the ALM,
LVDD, LBAT85, and LBAT75 status bits only. When ARST
bit is set to “1”, these status bits are reset to “0” after a valid
read of the respective status register (with a valid STOP
condition). When the ARST is cleared to “0”, the user must
manually reset the ALM, LVDD, LBAT85, and LBAT75 bits.
WRITE RTC ENABLE BIT (WRTC)
The WRTC bit enables or disables write capability into the
RTC Timing Registers. The factory default setting of this bit
is “0”. Upon initialization or power-up, the WRTC must be set
to “1” to enable the RTC. Upon the completion of a valid
write (STOP), the RTC starts counting. The RTC internal
1Hz signal is synchronized to the STOP condition during a
valid write cycle.
INTERRUPT/ALARM MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate
in the interrupt mode, where an active low pulse width of
250ms will appear at the IRQ/F
triggered by the alarm, as defined by the alarm registers
ADDR
DD
DD
08h
Trip1 and V
= 0V and V
TABLE 3. INTERRUPT CONTROL REGISTER (INT)
DD
ARST WRTC
DD
INDICATOR BIT (LV
7
or V
DD
BAT
BAT
6
Trip0 in PWR_V
= 0V). The bit is set regardless of
is applied first. The loss of only one of
DD
IM
5
has dropped below the
14
FOBATB FO3 FO2 FO1 FO0
OUT
DD
4
)
DD
pin when the RTC is
registers.
3
DD
2
Trip2,
1
0
ISL12022M
(0Ch to 11h). When the IM bit is cleared to “0”, the alarm will
operate in standard mode, where the IRQ/F
set low until the ALM status bit is cleared to “0”.
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)
This bit enables/disables the IRQ/F
backup mode (i.e. V
FOBATB is set to “1”, the IRQ/F
battery backup mode. This means that both the frequency
output and alarm output functions are disabled. When the
FOBATB is cleared to “0”, the IRQ/F
during battery backup mode. Note that the open drain
IRQ/F
operate in battery backup mode.
FREQUENCY OUT CONTROL BITS (FO <3:0>)
These bits enable/disable the frequency output function and
select the output frequency at the IRQ/F
for frequency selection. Default for the ISL12022M is
FO<3:0> = 1h, or 32.768kHz output (F
frequency mode is enabled, it will override the alarm mode at
the IRQ/F
FREQUENCY,
TABLE 5. FREQUENCY SELECTION OF IRQ/F
32768
F
4096
1024
1/16
1/32
IM BIT
OUT
1/2
1/4
1/8
OUT
64
32
16
0
8
4
2
1
0
1
OUT
pin will need a pull-up to the battery voltage to
pin.
UNITS
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Single Time Event Set By Alarm
Repetitive/Recurring Time Event Set By Alarm
BAT
INTERRUPT/ALARM FREQUENCY
power source active). When the
TABLE 4.
FO3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
OUT
OUT
OUT
FO2
pin is disabled during
OUT
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
OUT
pin during battery
pin is enabled
is ON). When the
OUT
pin. See Table 5
FO1
OUT
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
December 18, 2008
pin will be
PIN
FN6668.4
FO0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1