isl12022m Intersil Corporation, isl12022m Datasheet - Page 18

• Manufacturer Part Number: isl12022m
• Description: Real Time Clock With Embedded Crystal, ??5ppm Accuracy
• Manufacturer: Intersil Corporation

BETA VALUES = (AT(max) - AT (min))/63, where:
AT(max) = F
AT(min) = F
The BETA VALUES result is indexed in the right hand
column and the resulting Beta factor (for the register) is in
the same row in the left column.
The ISL12022M has a preset BETA value corresponding to
the crystal in the module. This value is recalled on initial
power-up and is preset in device production. It is READ
ONLY and cannot be overwritten by the user.
Final Analog Trimming Register (FATR)
This register shows the final setting of AT after temperature
correction. It is read-only; the user cannot overwrite a value to
this register. This value is accessible as a means of monitoring
the temperature compensation function. See Table 17 and
Table 12 (for values).
ADDR
0Eh
TABLE 17. FINAL ANALOG TRIMMING REGISTER
7
0
BETA<4:0>
OUT
OUT
01000
00110
00101
00100
00011
00010
00001
00000
10000
10001
10010
10011
10100
10101
10110
11000
11001
11010
00111
10111
11011
11100
11101
11110
11111
6
0
in ppm (at AT = 3FH).
in ppm (at AT = 00H) and
TABLE 16. BETA VALUES
FATR5 FATR4 FATR3 FATR2 FATR1 FATR0
5
18
4
AT STEP ADJUSTMENT
3
0.5000
0.5625
0.6250
0.6875
0.7500
0.8125
0.8750
0.9375
1.0000
1.0625
1.1250
1.1875
1.2500
1.3125
1.3750
1.4375
1.5000
1.5625
1.6250
1.6875
1.7500
1.8125
1.8750
1.9375
2.0000
2
1
ISL12022M
0
Final Digital Trimming Register (FDTR)
This Register shows the final setting of DT after temperature
correction. It is read-only; the user cannot overwrite a value
to this register. The value is accessible as a means of
monitoring the temperature compensation function. The
corresponding clock adjustment values are shown in
Table 19. The FDTR setting has both positive and negative
settings to adjust for any offset in the crystal.
.
ALARM Registers (10h to 15h)
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
ADDR
TABLE 19. CLOCK ADJUSTMENT VALUES FOR FINAL
0Fh
FDTR<2:0>
TABLE 18. FINAL DIGITAL TRIMMING REGISTER
00000
00001
00010
00011
00100
00101
00110
01000
01001
01010
10000
10001
10010
10011
10100
10101
10110
11000
11001
11010
00111
10111
7
0
DIGITAL TRIMMING REGISTER
6
0
5
0
FDTR4 FDTR3 FDTR2 FDTR1 FDTR0
4
DECIMAL
-10
10
-1
-2
-3
-4
-5
-6
-7
-8
-9
0
1
2
3
4
5
6
7
8
9
0
3
2
ADJUSTMENT
December 18, 2008
-152.5
-213.5
-274.5
152.5
213.5
274.5
-30.5
-91.5
ppm
-122
-183
-244
-305
30.5
91.5
122
183
244
305
-61
61
1
0
0
FN6668.4
0