cs4924 Cirrus Logic, Inc., cs4924 Datasheet - Page 3

• Manufacturer Part Number: cs4924
• Description: Multi-channel Digital Audio Decoders Logic
• Manufacturer: Cirrus Logic, Inc.

LIST OF FIGURES
LIST OF TABLES
DS262F2
7.
8.
9.
Figure 1.
Figure 2. Serial Compressed Data Timing ....................................................................................... 6
Figure 3. CLKIN with CLKSEL = VSS = PLL Enable........................................................................ 7
Figure 4. CLKIN with CLKSEL = VD = PLL Bypass ......................................................................... 7
Figure 5. Intel Parallel Host Mode Read Cycle................................................................................. 9
Figure 6. Intel Parallel Host Mode Write Cycle................................................................................. 9
Figure 7. Motorola Parallel Host Mode Read Cycle ....................................................................... 11
Figure 8. Motorola Parallel Host Mode Write Cycle........................................................................ 11
Figure 9. SPI Control Port Timing................................................................................................... 13
Figure 10. I
Figure 11. Digital Audio Input, Data and Clock Timing................................................................... 17
Figure 12. Digital Audio Output, Data and Clock Timing ................................................................ 19
Figure 13. I
Figure 14. I
Figure 15. SPI Control .................................................................................................................... 27
Figure 16. SPI Control with External Memory ................................................................................ 28
Figure 17. Intel Parallel Control Mode ............................................................................................ 29
Figure 18. Motorola Parallel Control Mode..................................................................................... 30
Figure 19. SPI Timing..................................................................................................................... 38
Figure 20. I
Figure 21. External Memory Interface ............................................................................................ 42
Figure 22. Run-Time Memory Access ............................................................................................ 42
Figure 23. Autoboot Timing Diagram.............................................................................................. 43
Figure 24. I
Figure 25. Left Justified Format...................................................................................................... 45
Figure 26. Right Justified................................................................................................................ 45
Figure 27. Multi-Channel Format (M == 20) ................................................................................... 45
Table 1. Silicon Revisions .............................................................................................................. 20
Table 2. Host Modes ...................................................................................................................... 33
Table 3. Host Memory Map ............................................................................................................ 34
Table 4. Intel Parallel Host Mode Pin Assignments........................................................................ 34
Table 5. Parallel Input/Output Registers......................................................................................... 35
Table 6. Motorola Parallel Host Mode Pin Assignments ................................................................ 36
Table 7. SPI Serial Mode Pin Assignments.................................................................................... 36
Table 8. I
Table 9. Memory Interface Pins...................................................................................................... 41
Table 10. Digital Audio Input Port................................................................................................... 46
Table 11. Compressed Data Input Port .......................................................................................... 46
Table 12. Digital Audio Output Port ................................................................................................ 47
Table 13. MCLK/SCLK Master Mode Ratios .................................................................................. 47
6.4 I
6.5 External Memory .............................................................................................................. 41
DIGITAL INPUT & OUTPUT .................................................................................................. 44
7.1 Digital Audio Formats ....................................................................................................... 44
7.2 Digital Audio Input Port .................................................................................................... 46
7.3 Compressed Data Input Port ........................................................................................... 46
7.4 Parallel Digital Audio Data Input ...................................................................................... 46
7.5 Digital Audio Output Port ................................................................................................. 47
PIN DESCRIPTIONS .............................................................................................................. 49
PACKAGE DIMENSIONS ...................................................................................................... 54
2
2
RESET Timing .................................................................................................................. 5
C Serial Host Interface .................................................................................................. 39
C Serial Mode Pin Assignments .................................................................................... 39
6.4.1
6.4.2
6.5.1
7.5.1
2
2
2
2
2
C Control Port Timing ................................................................................................. 15
C Control..................................................................................................................... 25
C Control with External Memory ................................................................................. 26
C Timing ..................................................................................................................... 40
S Format ..................................................................................................................... 45
I
I
External Memory and Autoboot ...................................................................... 43
IEC60958 Output ............................................................................................ 48
2
2
C Write ......................................................................................................... 39
C Read ......................................................................................................... 39
CS4923/4/5/6/7/8/9
3