cs4924 Cirrus Logic, Inc., cs4924 Datasheet - Page 38

• Manufacturer Part Number: cs4924
• Description: Multi-channel Digital Audio Decoders Logic
• Manufacturer: Cirrus Logic, Inc.

SCDOUT
INTREQ
SCCLK
SCDIN
CS
SCCLK
SCDIN
CS
AD6
AD6
AD5
AD5
Notes: 1. INTREQ is guaranteed to stay low until the rising edge of SCCLK for the second to last bit of
AD4
AD4
AD3 AD2 AD1 AD0 R/W
AD3 AD2 AD1 AD0 R/W
2. INTREQ is guaranteed to stay high until the next rising edge of SCCLK at which point it may
the last byte to be transferred out of the CS4923/4/5/6/7/8/9
go low again if there is new data to be read. The condition of INTREQ going low at this point
should be treated as a new read condition and a new start condition followed by an address
byte should be sent
D7
D7
D6
D6
D5
D5
D4
D4
SPI Write Functional Timing
SPI Read Functional Timing
D3
D3
Figure 19. SPI Timing
D2
D2
D1
D1
D0
D0
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
Note 1
D2
D2
D1
D1
D0
D0
Note 2