cs4924 Cirrus Logic, Inc., cs4924 Datasheet - Page 43

• Manufacturer Part Number: cs4924
• Description: Multi-channel Digital Audio Decoders Logic
• Manufacturer: Cirrus Logic, Inc.

Although the memory can use more address bits,
typically only 16 bits of address space are used. For
this
incorporates a 2 latch memory architecture.
The two latch external memory architecture is
required for the CS4926 or CS4928 when using
DTS. A three latch architecture can not be used
with the CS4926 or CS4928 running DTS since the
run time memory access uses only 2 address cycles.
6.5.1 External Memory and Autoboot
To
automatically load its code from external memory,
the ABOOT signal should be driven low at the
rising edge of RESET. Once again this mode can
only be chosen if either SPI or I
communication is being used. In serial control port
mode, holding the ABOOT pin low as the CS492X
leaves the reset state enables an automatic boot.
DS262F2
EMAD7:0
EXTMEM
configure
reason
ABOOT
RESET
EMWR
EMOE
the
the
memory
CS4923/4/5/6/7/8/9
example
Figure 23. Autoboot Timing Diagram
2
C serial
shown
MA23:16
to
ABOOT can be released following the rising edge
of RESET. During the automatic boot cycle, the
serial control port should remain idle. Figure 23
shows an autoboot functional timing example.
The autoboot cycle actually is a 24 bit, or three
address byte cycle. It should be noted that for
autoboot, the most significant byte is always zero.
For this reason a two latch external memory
configuration can be used for autoboot. The higher
order address byte simply shifts out of the memory
latch and is discarded. If desired, a three latch
interface
CS4923/4/5/7/9 but it is not necessary.
For more information about autoboot and for a
thorough description of different external memory
architectures, reference the CS4923/4/5/6/7/8/9
Hardware User’s Guide.
MA15:8
could
also
CS4923/4/5/6/7/8/9
MA7:0
be
used
Data7:0
with
the
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