cs4924 Cirrus Logic, Inc., cs4924 Datasheet - Page 8

• Manufacturer Part Number: cs4924
• Description: Multi-channel Digital Audio Decoders Logic
• Manufacturer: Cirrus Logic, Inc.

SWITCHING CHARACTERISTICS—INTEL
(T
Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can
8
Address setup before CS and RD low or CS and WR low
Address hold time after CS and RD low or CS and WR low
Delay between RD then CS low or CS then RD low
Data valid after CS and RD low
CS and RD low for read
Data hold time after CS or RD high
Data high-Z after CS or RD high
CS or RD high to CS and RD low for next read
CS or RD high to CS and WR low for next write
Delay between WR then CS low or CS then WR low
Data setup before CS or WR high
CS and WR low for write
Data hold after CS or WR high
CS or WR high to CS and RD low for next read
CS or WR high to CS and WR low for next write
A
= 25 C; VA, VD = 3.3 V 5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C
2. This specification is characterized but not production tested.
be defined as follows:
External CLKIN Mode:
DCLK == CLKIN/3 before and during boot
DCLK == CLKIN after boot
Internal Clock Mode:
DCLK == 10MHz before and during boot, i.e. DCLK == 100ns
DCLK == 60 MHz after boot, i.e. DCLK == 16.7ns (this speed may depend on CLKIN, please see
CS4923/4/5/6/7/8/9 Hardware User’s Guide for more information)
Parameter
(Note 1)
(Note 2)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
®
HOST MODE
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
iwpw
irdtw
idhw
iwtrd
icdw
irpw
idsu
icdr
idhr
idis
iwd
iah
idd
ias
ird
L
2*DCLK + 10
2*DCLK + 10
2*DCLK + 10
2*DCLK + 10
DCLK + 10
DCLK + 10
= 20 pF)
Min
20
5
5
0
5
0
5
-
-
CS4923/4/5/6/7/8/9
Max
20
15
-
-
-
-
-
-
-
-
-
-
-
DS262F2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns