cs4924 Cirrus Logic, Inc., cs4924 Datasheet - Page 39

• Manufacturer Part Number: cs4924
• Description: Multi-channel Digital Audio Decoders Logic
• Manufacturer: Cirrus Logic, Inc.

6.4 I
For I
always acts as a slave. Serial I
with the CS4923/4/5/6/7/8/9 is accomplished with
3 communication lines: SCCLK, SCDIO and
INTREQ. Table 8 shows the mnemonic, pin name,
and pin number of each signal on the
CS4923/4/5/6/7/8/9. SCCLK is an input to the
CS492X that clocks data in and out of the device on
its rising edge. It should be noted that the timing
specifications for SCCLK are more stringent than
certain I
that the rise and fall specifications for SCCLK are
met as stated in the timing portion of this data sheet.
SCDIO is a bidirectional data line whose data must
be valid on the rising edge of SCCLK. INTREQ is
an open drain, active-low request signal that is
driven low by the CS492X when there is data to be
read out.
6.4.1 I
When writing to the device in I
protocol can be used for sending a byte, a word or
an entire download image as long as transfers occur
on byte boundaries. Figure 20 illustrates the
relative timing necessary for a three byte transfer to
the CS492X. The host initiates a transfer with an
I
the read/write bit set low to indicate a write. The
start condition is defined as the SCDIO falling with
SCCLK held high. The CS492X internal 7-bit
address is initially assigned to 000 0000b following
a reset. The 7-bit address sent to the CS492X must
match its internal address or the incoming data will
be ignored. Address checking can be disabled or
DS262F2
SCCLK
SCDIO
INTREQ
2
Pin Name
C start condition followed by a 7-bit address and
2
C communications the CS4923/4/5/6/7/8/9
Table 8. I
2
C Serial Host Interface
2
2
C requirements so care should be taken
C Write
Serial Data Input and
2
Serial Control Clock
C Serial Mode Pin Assignments
Interrupt Request
Pin Description
Output
2
C communication
2
C, the same
Pin Number
19
20
7
the actual address can be changed if desired.
Address checking configuration is documented in
the hardware configuration section of the
CS4923/4/5/6/7/8/9 Hardware User’s guide. After
the address byte the host should then clock an
acknowledge (ACK) from the part. During a write,
an ACK is defined as SCDIO being driven low by
the CS492X for one SCCLK period after each byte.
Data should be shifted into the CS492X most
significant byte first with data being valid at the rising
edge of SCCLK. The host should then clock out the
acknowledge (ACK bit) bit from the CS492X. After
the last byte to be sent is acknowledged, the host
should send an I
the rising edge of SCDIO while SCCLK is held high.
If the CS492X fails to acknowledge a byte, the host
should re-transmit the same byte. If the CS492X
does not acknowledge back to back bytes, then the
host should reset the part.
6.4.2 I
The CS4923/4/5/6/7/8/9 will always indicate that it
has data to be read by asserting the INTREQ line
low. The host must recognize the request and start a
read transaction with the CS492X. The same
protocol will be used whether reading a byte or
multiple bytes. Figure 20 also illustrates the relative
timing of a three byte I
The host initiates a read with an I
followed by a 7-bit address and the read/write bit set
high for a read. The start condition is defined as the
SCDIO falling with SCCLK held high. The CS492X
internal 7-bit address is initially assigned to 000
0000b following a reset. The 7-bit address sent to the
CS492X must match its internal address or the
incoming data will be ignored. Address checking
can be disabled or the actual address can be changed
if desired. Address checking configuration is
documented in the hardware configuration section
of the CS4923/4/5/6/7/8/9 Hardware User’s guide.
2
C Read
2
C stop condition, which is defined as
CS4923/4/5/6/7/8/9
2
C read.
2
C start condition
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