cs4924 Cirrus Logic, Inc., cs4924 Datasheet - Page 40

• Manufacturer Part Number: cs4924
• Description: Multi-channel Digital Audio Decoders Logic
• Manufacturer: Cirrus Logic, Inc.

SCCLK
SCDIO
SCCLK
SCDIO
INTREQ
I2C Start
I2C Start
AD6
AD6
AD5
AD5
AD4
AD4
Notes: 1. The ACK for the address byte is driven by the CS4923/4/5/6/7/8/9.
AD3 AD2 AD1 AD0 R/W
AD3 AD2 AD1 AD0 R/W
2. The ACKs for the data bytes being read from the CS4923/4/5/6/7/8/9 should be driven by the
3. INTREQ is guaranteed to stay low until the rising edge of SCCLK for last bit of the last byte to
4. A NOACK should be sent by the host after the last byte read to indicate the end of the read
5. INTREQ is guaranteed to stay high until the next rising edge of SCCLK (for the ACK/NACK
host.
be transferred out of the CS4923/4/5/6/7/8/9
cycle.
bit) at which point it may go low again if there is new data to be read. The condition of INTREQ
going low at this point should be treated as a new read condition and a new start condition
followed by an address byte should be sent.
ACK
Note 1
ACK
D7
D7
D6
D6
D5
D5
D4
I2C Write Functional Timing
D4
I2C Read Functional Timing
D3
D3
D2
Figure 20. I
D2
D1
D1
D0
D0
ACK
ACK
2
C Timing
D7
D7
D6
D6
D5
D5
D4
Note 2
D4
D3
D3
D2
D2
D1
D1
D0
D0
ACK
ACK
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
Note 3
D1
D1
D0
Note 4
D0
ACK
NACK
I2C Stop
Note 5
I2C Stop