t6020m ATMEL Corporation, t6020m Datasheet - Page 27

• Manufacturer Part Number: t6020m
• Description: Low-current Microcontroller For Watchdog Function
• Manufacturer: ATMEL Corporation

Timer 1 Control Register 1 (T1C1)
The three bits T1C[2:0] select the divider for timer 1. The
resulting time interval depends on this divider and the
timer 1 input clock source. The timer input can be sup-
plied by the system clock or via the clock management.
Tin: input clock period = 1/Cin (see figure 14)
Timer 1 Control Register 2 (T1C2)
Rev. A3, 02-Apr-01
T1C1
T1RM
T1C2
T1C1
T1C0
T1C2
T1BP
T1CS
T1IM
T1C2
0
0
0
0
1
1
1
1
Timer 1 Restart Mode
Note: if WDL = 0, Timer 1 restart is impossible
Timer 1 Control bit 2
Timer 1 Control bit 1
Timer 1 Control bit 0
Timer 1 SUBCL ByPassed
T1BP = 1, TIOUT = T1MUX
T1BP = 0, T1OUT = SUBCL
Timer 1 input Clock Select
T1CS = 1, CL1 = SUBCL (see figure 28)
T1CS = 0, CL1 = SYSCL (see figure 28)
Timer 1 Interrupt Mask
T1IM = 1, disables Timer 1 interrupt
T1IM = 0, enables Timer 1 interrupt
T1C1
0
0
1
1
0
0
1
1
* Bit 3 –> MSB, Bit 0 –> LSB
* Bit 3 –> MSB, Bit 0 –> LSB
Bit 3 *
T1RM
Bit 3 *
– – –
T1C0
0
1
0
1
0
1
0
1
T1BP
T1C2
Bit 2
Bit 2
Divider
16384
2048
256
16
32
2
4
8
T1RM = 0, write access without Timer 1 restart
T1RM = 1, write access with Timer 1 restart
T1C1
T1CS
Time Interval with SUBCL from Clock
Bit 1
Bit 1
Tin
Tin
T1IM
T1C0
Management
If the clock management generates the SUBCL, the se-
lected input clock from the RC oscillator or an external
clock is divided by 16.
Bit 0
Tin
Bit 0
Tin
Tin
Tin
Tin
Tin
262144
32768
4096
128
256
512
32
64
Address: ’7’hex – Subaddress: ’8’hex
Address: ’7’hex – Subaddress: ’9’hex
Time Interval with SYSCL = 2/1
8192 ms / 16384 ms
1024 ms / 2048 ms
128 ms / 256 ms
T6020M
16 ms / 32 ms
8 ms / 16 ms
Reset value: x111b
Reset value: 1111b
1 ms / 2 ms
2 ms / 4 ms
4 ms / 8 ms
MHz
27 (54)