t6020m ATMEL Corporation, t6020m Datasheet - Page 39

• Manufacturer Part Number: t6020m
• Description: Low-current Microcontroller For Watchdog Function
• Manufacturer: ATMEL Corporation

External SSI clocking is not supported in these modes.
The SSI should thus generate and has full control over the
shift clock so that it can always be regarded as an I
Master device.
All directional control of the external data port used by
the SSI is handled automatically and is dependent on the
transmission direction set by the Serial Data Direction
(SDD) control bit. This control bit defines whether the
SSI is currently operating in Transmit (TX) mode or
Receive (RX) mode.
Serial data is organized in 8-bit telegrams which are
shifted with the most significant bit first. In the 9-bit I
mode, an additional acknowledge bit is appended to the
end of the telegram for handshaking purposes (see I
protocol).
At the beginning of every telegram, the SSI control loads
the transmit buffer into the shift register and proceeds
immediately to shift data serially out. At the same time,
incoming data is shifted into the shift register input. This
incoming data is automatically loaded into the receive
buffer when the complete telegram has been received.
Data can, if required thus be simultaneously received and
transmitted.
Before data can be transferred, the SSI must first be
activated. This is performed by means of the SSI reset
control (SIR) bit. All further operation then depends on
the data directional mode (TX/RX) and the present status
of the SSI buffer registers shown by the Serial Interface
Ready Status Flag (SRDY). This SRDY flag indicates the
(empty/full) status of either the transmit buffer (in TX
mode), or the receive buffer (in RX mode). The control
logic ensures that data shifting is temporarily halted at
any time, if the appropriate receive/transmit buffer is not
ready (SRDY = 0). The SRDY status will then
automatically be set back to ‘1’ and data shifting resumed
as soon as the application software loads the new data into
the transmit register (in TX mode) or frees the shift
register by reading it into the receive buffer (in RX mode).
A further activity status (ACT) bit indicates the present
status of the serial communication. The ACT bit remains
high for the duration of the serial telegram or if I
or start conditions are currently being generated. Both the
current SRDY and ACT status can be read in the SSI
status register. To deactivate the SSI, the SIR bit must be
set high.
Rev. A3, 02-Apr-01
2
2
C stop
C Bus
2
2
C
C
8-bit Synchronous Mode
(falling edge)
In the 8-bit synchronous mode, the SSI can operate as
either a 2 or 3 wire interface (see SSI peripheral
configuration). The serial data (SD) is received or
transmitted in NRZ format, synchronised to either the
rising or falling edge of the shift clock (SC). The choice
of clock edge is defined by the Serial Mode Control bits
(SM0,SM1). It should be noted that the transmission edge
refers to the SC clock edge with which the SD changes.
To avoid clock skew problems, the incoming serial input
data is shifted in with the opposite edge.
When used together with one of the timer modulator or
demodulator stages, the SSI must be set in the 8-bit
synchronous mode 1.
In RX mode, as soon as the SSI is activated (SIR= 0), 8
shift clocks are generated and the incoming serial data is
shifted into the shift register. This first telegram is
automatically transferred into the receive buffer and the
SRDY set to 0 indicating that the receive buffer contains
valid data. At the same time an interrupt (if enabled) is
generated. The SSI then continues shifting in the
following 8-bit telegram. If, during this time the first
telegram has been read by the controller, the second
telegram will also be transferred in the same way into the
receive buffer and the SSI will continue clocking in the
next telegram. Should, however, the first telegram not
have been read
temporarily holding the second telegram in the shift
register until a certain point of time when the controller
is able to service the receive buffer. In this way no data is
lost or overwritten.
Deactivating the SSI (SIR=1) in mid–telegram will
immediately stop the shift clock and latch the present
contents of the shift register into the receive buffer. This
can be used for clocking in a data telegram of less than 8
bits in length. Care should be taken to read out the final
complete 8-bit data telegram of a multiple word message
before deactivating the SSI (SIR=1) and terminating the
reception. After termination, the shift register contents
will overwrite the receive buffer.
(rising edge)
SD/TO2
DATA
SC
SC
Data: 00110101
Bit 7
Bit 7
0
0
Figure 41. 8-bit synchronous mode
0
0
(SRDY=1), then the SSI will stop,
1
1
1
1
0
0
T6020M
1
1
0
0
39 (54)
Bit 0
Bit 0
1
1
13823