ltc2182 Linear Technology Corporation, ltc2182 Datasheet - Page 16

• Manufacturer Part Number: ltc2182
• Description: 16-bit, 65msps/ 40msps/25msps Low Power Dual Adcs
• Manufacturer: Linear Technology Corporation

LTC2182/LTC2181/LTC2180
PIN FUNCTIONS
PINS THAT ARE THE SAME FOR ALL DIGITAL
OUTPUT MODES
V
1.9V. Bypass to ground with 0.1µF ceramic capacitors.
Adjacent pins can share a bypass capacitor.
V
to V
of the analog inputs to channel 1. Bypass to ground with
a 0.1µF ceramic capacitor.
GND (Pins 3, 6, 14): ADC Power Ground.
A
Input.
A
Input.
REFH (Pins 7, 9): ADC High Reference. See the Applica-
tions Information section for recommended bypassing
circuits for REFH and REFL.
REFL (Pins 8, 10): ADC Low Reference. See the Applica-
tions Information section for recommended bypassing
circuits for REFH and REFL.
PAR/SER (Pin 11): Programming mode selection pin. Con-
nect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to V
parallel programming mode where CS, SCK, SDI, SDO
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directly to ground or V
A
Input.
A
Input.
V
equal to V
mode of the analog inputs to channel 2. Bypass to ground
with a 0.1µF ceramic capacitor.
ENC
rising edge.
16
DD
CM1
IN1
IN1
IN2
IN2
CM2
DD
+
–
+
–
+
(Pins 1, 16, 17, 64): Analog Power Supply, 1.7V to
(Pin 2): Common Mode Bias Output, nominally equal
(Pin 15): Common Mode Bias Output, nominally
(Pin 18): Encode Input. Conversion starts on the
(Pin 13): Channel 2 Negative Differential Analog
/2. V
(Pin 5): Channel 1 Negative Differential Analog
(Pin 12): Channel 2 Positive Differential Analog
(Pin 4): Channel 1 Positive Differential Analog
DD
CM1
/2. V
should be used to bias the common mode
CM2
DD
should be used to bias the common
and not be driven by a logic signal.
DD
to enable the
ENC
starts on the falling edge. Tie to GND for single-ended
encode mode.
CS (Pin 20): In serial programming mode, (PAR/SER =
0V), CS is the Serial Interface Chip Select Input. When CS
is low, SCK is enabled for shifting data on SDI into the
mode control registers. In the parallel programming mode
(PAR/SER = V
(See Table 2). CS can be driven with 1.8V to 3.3V logic.
SCK (Pin 21): In serial programming mode, (PAR/SER =
0V), SCK is the Serial Interface Clock Input. In the parallel
programming mode (PAR/SER = V
digital output mode. (See Table 2). SCK can be driven with
1.8V to 3.3V logic.
SDI (Pin 22): In serial programming mode, (PAR/SER =
0V), SDI is the Serial Interface Data Input. Data on SDI
is clocked into the mode control registers on the rising
edge of SCK. In the parallel programming mode (PAR/
SER = V
down the part (see Table 2). SDI can be driven with 1.8V
to 3.3V logic.
OGND (Pin 41): Output Driver Ground. Must be shorted
to the ground plane by a very low inductance path. Use
multiple vias close to the pin.
OV
with a 0.1µF ceramic capacitor.
SDO (Pin 61): In serial programming mode, (PAR/SER
= 0V), SDO is the optional Serial Interface Data Output.
Data on SDO is read back from the mode control regis-
ters and can be latched on the falling edge of SCK. SDO
is an open-drain NMOS output that requires an external
2k pull-up resistor to 1.8V – 3.3V. If read back from the
mode control registers is not needed, the pull-up resistor
is not necessary and SDO can be left unconnected. In the
parallel programming mode (PAR/SER = V
be used together with SDI to power down the part (see
Table 2). When used as an input, SDO can be driven with
1.8V to 3.3V logic through a 1k series resistor.
V
ground with a 2.2µF ceramic capacitor. The output voltage
is nominally 1.25V.
REF
DD
–
(Pin 62): Reference Voltage Output. Bypass to
(Pin 19): Encode Complement Input. Conversion
(Pin 42): Output Driver Supply. Bypass to ground
DD
), SDI can be used together with SDO to power
DD
), CS controls the clock duty cycle stabilizer
DD
), SCK controls the
DD
), SDO can
218210f