ltc2182 Linear Technology Corporation, ltc2182 Datasheet - Page 22

• Manufacturer Part Number: ltc2182
• Description: 16-bit, 65msps/ 40msps/25msps Low Power Dual Adcs
• Manufacturer: Linear Technology Corporation

LTC2182/LTC2181/LTC2180
22
APPLICATIONS INFORMATION
ENC
ENC
+
–
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
0.1µF
0.1µF
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
1.8V TO 3.3V
Figure 13. PECL or LVDS Encode Drive
LTC2182
PECL OR
Figure 12. Sinusoidal Encode Drive
CLOCK
LVDS
15k
30k
0V
T1
V
DD
0.1µF
0.1µF
50Ω
50Ω
V
DD
ENC
ENC
ENC
ENC
+
–
LTC2182
+
–
0.1µF
30k
100Ω
LTC2182
DIFFERENTIAL
COMPARATOR
ENC
ENC –
CMOS LOGIC
218210
BUFFER
+
F13
218210 F10
218210
LTC2182
F11
218210 F12
mode, ENC
avoid falsely triggering the single ended encode mode.
For good jitter performance ENC
fast rise and fall times.
The single-ended encode mode should be used with CMOS
encode inputs. To select this mode, ENC
to ground and ENC
input. ENC
to 3.3V CMOS logic levels can be used. The ENC
is 0.9V. For good jitter performance ENC
rise and fall times.
If the encode signal is turned off or drops below approxi-
mately 500kHz, the A/D enters nap mode.
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50% (±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency, the duty cycle stabilizer circuit
requires one hundred clock cycles to lock onto the input
clock. The duty cycle stabilizer is enabled by mode control
register A2 (serial programming mode), or by CS (parallel
programming mode).
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken to
make the sampling clock have a 50% (±5%) duty cycle. The
duty cycle stabilizer should not be used below 5Msps.
DIGITAL OUTPUTS
Digital Output Modes
The LTC2182/LTC2181/LTC2180 can operate in three digital
output modes: full rate CMOS, double data rate CMOS (to
halve the number of output lines), or double data rate LVDS
(to reduce digital noise in the system.) The output mode
is set by mode control register A3 (serial programming
mode), or by SCK (parallel programming mode). Note that
double data rate CMOS cannot be selected in the parallel
programming mode.
+
–
can be taken above V
should stay at least 200mV above ground to
+
is driven with a square wave encode
+
DD
and ENC
(up to 3.6V) so 1.8V
+
should have fast
–
–
is connected
should have
+
threshold
218210f