ltc2182 Linear Technology Corporation, ltc2182 Datasheet - Page 23

• Manufacturer Part Number: ltc2182
• Description: 16-bit, 65msps/ 40msps/25msps Low Power Dual Adcs
• Manufacturer: Linear Technology Corporation

Full Rate CMOS Mode
In full rate CMOS mode the data outputs (D1_0 to D1_15
and D2_0 to D2_15), overflow (OF2, OF1), and the data
output clocks (CLKOUT
levels. The outputs are powered by OV
are isolated from the A/D core power and ground. OV
can range from 1.1V to 1.9V, allowing 1.2V through 1.8V
CMOS logic outputs.
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
Double Data Rate CMOS Mode
In Double Data Rate CMOS mode, two data bits are multi-
plexed and output on each data pin. This reduces the num-
ber of digital lines by seventeen, simplifying board routing
and reducing the number of input pins needed to receive
the data. The data outputs (D1_0_1, D1_2_3, D1_4_5,
D1_6_7, D1_8_9, D1_10_11, D1_12_13, D1_14_15,
D2_0_1, D2_2_3, D2_4_5, D2_6_7, D2_8_9, D2_10_11,
D2_12_13, D2_14_15), overflow (OF2_1), and the data
output clocks (CLKOUT
levels. The outputs are powered by OV
are isolated from the A/D core power and ground. OV
can range from 1.1V to 1.9V, allowing 1.2V through 1.8V
CMOS logic outputs. Note that the overflow for both ADC
channels is multiplexed onto the OF2_1 pin.
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
Double Data Rate LVDS Mode
In double data rate LVDS mode, two data bits are multi-
plexed and output on each differential output pair. There
are eight LVDS output pairs per ADC channel (D1_0_1
D1_0_1
D2_0_1
output data. Overflow (OF2_1
APPLICATIONS INFORMATION
–
–
through D1_14_15
through D2_14_15
+
+
, CLKOUT
, CLKOUT
+
+
/D1_14_15
/D2_14_15
+
/OF2_1
–
–
) have CMOS output
) have CMOS output
DD
DD
–
and OGND which
and OGND which
–
–
) and the data
) for the digital
and D2_0_1
DD
DD
+
+
/
/
output clock (CLKOUT
output pair. Note that the overflow for both ADC channels
is multiplexed onto the OF2_1
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OV
isolated from the A/D core power and ground. In LVDS
mode, OV
Programmable LVDS Output Current
In LVDS mode, the default output driver current is 3.5mA.
This current can be adjusted by serially programming mode
control register A3. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Optional LVDS Driver Internal Termination
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing.
Overflow Bit
The overflow output bit outputs a logic high when the
analog input is either over-ranged or under-ranged. The
overflow bit has the same pipeline latency as the data bits.
In Full-Rate CMOS mode each ADC channel has its own
overflow pin (OF1 for channel 1, OF2 for channel 2). In
DDR CMOS or DDR LVDS mode the overflow for both ADC
channels is multiplexed onto the OF2_1 output.
LTC2182/LTC2181/LTC2180
DD
must be 1.8V.
+
/CLKOUT
+
/OF2_1
DD
–
) each have an LVDS
and OGND which are
–
output pair.
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