s908gr32ag3vfa Freescale Semiconductor, Inc, s908gr32ag3vfa Datasheet - Page 169

• Manufacturer Part Number: s908gr32ag3vfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

RE — Receiver Enable Bit
RWU — Receiver Wakeup Bit
SBK — Send Break Bit
13.8.3 ESCI Control Register 3
ESCI control register 3 (SCC3):
R8 — Received Bit 8
Freescale Semiconductor
Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not
affect receiver interrupt flag bits. Reset clears the RE bit.
This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled.
The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out
of the standby state and clears the RWU bit. Reset clears the RWU bit.
Setting and then clearing this read/write bit transmits a break character followed by a 1. The 1 after the
break character guarantees recognition of a valid start bit. If SBK remains set, the transmitter
continuously transmits break characters with no 1s between them. Reset clears the SBK bit.
•
•
When the ESCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received
character. R8 is received at the same time that the SCDR receives the other 8 bits.
1 = Receiver enabled
0 = Receiver disabled
1 = Standby state
0 = Normal operation
1 = Transmit break characters
0 = No break characters being transmitted
Stores the ninth ESCI data bit received and the ninth ESCI data bit to be transmitted.
Enables these interrupts:
–
–
–
–
Receiver overrun
Noise error
Framing error
Parity error
Address:
Writing to the RE bit is not allowed when the enable ESCI bit (ENSCI) is
clear. ENSCI is in ESCI control register 1.
Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling
SBK before the preamble begins causes the ESCI to send a break
character instead of a preamble.
Reset:
Read:
Write:
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
$0015
Bit 7
R8
U
Figure 13-12. ESCI Control Register 3 (SCC3)
= Unimplemented
T8
6
0
R
5
0
NOTE
NOTE
R
R
4
0
= Reserved
ORIE
3
0
NEIE
U = Unaffected
2
0
FEIE
1
0
PEIE
Bit 0
0
I/O Registers
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