s908gr32ag3vfa Freescale Semiconductor, Inc, s908gr32ag3vfa Datasheet - Page 250

• Manufacturer Part Number: s908gr32ag3vfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Timer Interface Module (TIM2)
18.3.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use the following
initialization procedure:
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM2
channel 0 registers (T2CH0H:T2CH0L) initially control the buffered PWM output. TIM2 status control
register 0 (T2SC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority
over MS0A.
Setting MS2B links channels 2 and 3 and configures them for buffered PWM operation. The TIM2
channel 2 registers (T2CH2H:T2CH2L) initially control the buffered PWM output. TIM2 status control
register 2 (T2SC2) controls and monitors the PWM signal from the linked channels. MS2B takes priority
over MS2A.
Setting MS4B links channels 4 and 5 and configures them for buffered PWM operation. The TIM2
channel 4 registers (T2CH4H:T2CH4L) initially control the buffered PWM output. TIM2 status control
register 4 (T2SC4) controls and monitors the PWM signal from the linked channels. MS4B takes priority
over MS4A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM2 overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
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1. In the TIM2 status and control register (T2SC):
2. In the TIM2 counter modulo registers (T2MODH:T2MODL), write the value for the required PWM
3. In the TIM2 channel x registers (T2CHxH:T2CHxL), write the value for the required pulse width.
4. In TIM2 channel x status and control register (T2SCx):
5. In the TIM2 status control register (T2SC), clear the TIM2 stop bit, TSTOP.
period.
a. Stop the TIM2 counter by setting the TIM2 stop bit, TSTOP.
b. Reset the TIM2 counter and prescaler by setting the TIM2 reset bit, TRST.
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (polarity 1 — to clear output on compare) or 1:1 (polarity 0 — to set output on
or PWM signals) to the mode select bits, MSxB:MSxA. (See
compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must
force the output to the complement of the pulse width level. (See
In buffered PWM signal generation, do not write pulse width values to the
currently active channel registers. User software should track the currently
active channel to prevent writing a new value to the active channel. Writing
to the active channel registers is the same as generating unbuffered PWM
signals.
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
NOTE
NOTE
Table
Table
18-2.)
Freescale Semiconductor
18-2.)