s908gr32ag3vfa Freescale Semiconductor, Inc, s908gr32ag3vfa Datasheet - Page 256

• Manufacturer Part Number: s908gr32ag3vfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Timer Interface Module (TIM2)
CHxF — Channel x Flag Bit
CHxIE — Channel x Interrupt Enable Bit
MSxB — Mode Select Bit B
MSxA — Mode Select Bit A
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When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM2 counter registers matches the value in the TIM2 channel x registers.
When CHxIE = 1, clear CHxF by reading TIM2 channel x status and control register with CHxF set,
and then writing a 0 to CHxF. If another interrupt request occurs before the clearing sequence is
complete, then writing 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to
inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
This read/write bit enables TIM2 CPU interrupts on channel x.
Reset clears the CHxIE bit.
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM2
channel 0, TIM2 channel 2, and TIM2 channel 4 status and control registers.
Setting MS0B disables the channel 1 status and control register and reverts T2CH1 pin to
general-purpose I/O.
Setting MS2B disables the channel 3 status and control register and reverts T2CH3 pin to
general-purpose I/O.
Setting MS4B disables the channel 5 status and control register and reverts T2CH5 pin to
general-purpose I/O.
Reset clears the MSxB bit.
When ELSxB:ELSxA ≠ 00, this read/write bit selects either input capture operation or unbuffered
output compare/PWM operation. (See
When ELSxB:ELSxA = 00, this read/write bit selects the initial output level of the T2CHx pin once
PWM, input capture, or output compare operation is enabled. (See
bit.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
1 = Initial output level low
0 = Initial output level high
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIM2 status and control register (T2SC).
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Table
18-2.)
NOTE
Table
18-2.) Reset clears the MSxA
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