mpc9315far2 Integrated Device Technology, mpc9315far2 Datasheet - Page 10

• Manufacturer Part Number: mpc9315far2
• Description: 2.5v And 3.3v Lvcmos Pll Clock Generator
• Manufacturer: Integrated Device Technology

IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9315
2.5 V and 3.3 V CMOS PLL Clock Generator and Driver
10
Power Supply Filtering
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Noise on the
V
for instance I/O jitter. The MPC9315 provides separate power
supplies for the output buffers (V
loop (V
technique is to isolate the high switching noise digital outputs
from the relatively sensitive internal analog phase-locked
loop. In a digital system environment where it is more difficult
to minimize noise on the power supplies, a second level of
isolation may be required. The simple but effective form of
isolation is a power supply filter on the V
MPC9315.
scheme. The MPC9315 frequency and phase stability is most
susceptible to noise with spectral content in the 100 kHz to 20
MHz range. Therefore the filter should be designed to target
this range. The key parameter that needs to be met in the
final filter design is the DC voltage drop across the series filter
resistor R
sourced through the V
maximum), assuming that a minimum of 2.325 V (V
3.3 V or V
The resistor R
270 Ω (V
voltage drop criteria.
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in
3-5 kHz and the noise attenuation at 100 kHz is better than
42 dB.
MPC9315
CCA
The MPC9315 is a mixed analog/digital product. Its analog
R
R
The minimum values for R
F
F
V
= 9–10 Ω for V
= 270 Ω for V
CC
(PLL) power supply impacts the device characteristics,
CCA
CC
F
CC
. From the data sheet, the I
Figure 10. V
) of the device. The purpose of this design
Figure 10
= 3.3 V) or 9-10 Ω (V
= 2.5 V) must be maintained on the V
F
Figure
shown in
CC
CC
R
= 3.3 V
F
10, the filter cut-off frequency is around
illustrates a typical power supply filter
= 2.5 V
CCA
CCA
C
Figure 10
F
pin) is typically 3 mA (5 mA
Power Supply Filter
33...100 nF
F
and the filter capacitor C
10 nF
CC
C
C
CC
F
F
must have a resistance of
) and the phase-locked
= 22 µF for V
= 1 µF for V
= 2.5 V) to meet the
CCA
CCA
current (the current
V
V
CCA
CC
pin for the
CC
CC
MPC9315
= 3.3 V
= 2.5 V
CCA
CC
=
F
pin.
are
10
of an individual capacitor, its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9315 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise-related problems in most designs.
Driving Transmission Lines
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20 Ω, the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines, the reader is referred to Freescale application note
AN1091. In most high performance clock networks,
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50 Ω resistance to V
thus only a single terminated line can be driven by each
output of the MPC9315 clock driver. For the series terminated
case, however, there is no DC current draw; thus, the outputs
can drive multiple series terminated lines.
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken to
its extreme, the fanout of the MPC9315 clock driver is
effectively doubled due to its capability to drive multiple lines.
results of an output driving a single line versus two lines. In
As the noise frequency crosses the series resonant point
The MPC9315 clock driver was designed to drive high
This technique draws a fairly high level of DC current and
IN
IN
The waveform plots in
Figure 11. Single versus Dual Transmission Lines
MPC9315
MPC9315
Output
Output
Buffer
Buffer
14Ω
14Ω
CC
÷2.
R
R
R
S
S
S
Figure 11
= 36Ω
= 36Ω
= 36Ω
Advanced Clock Drivers Devices
Freescale Semiconductor
show the simulation
Z
Z
Z
O
O
O
= 50Ω
= 50Ω
= 50Ω
Figure 11
OutA
OutB0
OutB1
NETCOM
MPC9315