mpc9315far2 Integrated Device Technology, mpc9315far2 Datasheet - Page 3

• Manufacturer Part Number: mpc9315far2
• Description: 2.5v And 3.3v Lvcmos Pll Clock Generator
• Manufacturer: Integrated Device Technology

IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9315
2.5 V and 3.3 V CMOS PLL Clock Generator and Driver
Advanced Clock Drivers Devices
Freescale Semiconductor
Table 1. Pin Configuration
Table 2. Function Table
Table 3. Absolute Maximum Ratings
CLK0
CLK1
FB0
FB1
REF_SEL
FB_SEL
FSELA
FSELB
FSELC
PSELA
QA0, QA1
QB0 to QB3
QC0, QC1
OE
V
V
GND
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
Symbol
CCA
CC
V
REF_SEL
V
I
V
OUT
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated
conditions is not implied.
FB_SEL
Control
OUT
I
T
FSELA
FSELB
FSELC
PSELA
IN
CC
IN
V
S
MR
OE
CCA
Pin
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage temperature
Default
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Input
none
0
0
0
1
1
0
0
0
CLK0
FB0
QAx = VCO clock frequency
QBx = VCO clock frequency
QCx = VCO clock frequency ÷ 2
0° (QA0, QA1 non-inverted)
V
Normal operation
Outputs enabled
CCA
Characteristics
I/O
= GND, PLL off and bypassed for static test and diagnosis V
(1)
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Supply
Supply
Ground
Type
0
3
Reference clock input
Alternative clock input
PLL feedback input
Alternative feedback input
Selects clock input reference clock input, default low (pull-down)
Selects PLL feedback clock input, default low (pull-down)
Selects divider ratio of bank A outputs, default low (pull-down)
Selects divider ratio of bank B outputs, default low (pull-up)
Selects divider ratio of bank C outputs, default low (pull-up)
Selects phase of bank A outputs
Bank A outputs
Bank B outputs
Bank C outputs
Output tristate
Analog (PLL) positive supply voltage. Requires external RC filter
Digital positive supply voltage
Digital negative supply voltage (ground)
Min
-0.3
-0.3
-0.3
-55
CLK1
FB1
QA0, QA1 = VCO clock frequency ÷ 2
QB0 - QB3 = VCO clock frequency ÷ 2
QC0, QC1 = VCO clock frequency ÷ 4
180° (QA0, QA1 inverted)
Reset (VCO clamped to min. range)
Outputs disabled (tristate), open PLL loop
V
V
CCA
CC
CC
Max
±20
±50
125
4.6
+0.3
+0.3
Function
= 3.3 or 2.5 V, PLL enabled
Unit
mA
mA
°C
V
V
V
1
Condition
MPC9315
NETCOM
MPC9315
3