mpc9315far2 Integrated Device Technology, mpc9315far2 Datasheet - Page 7

• Manufacturer Part Number: mpc9315far2
• Description: 2.5v And 3.3v Lvcmos Pll Clock Generator
• Manufacturer: Integrated Device Technology

IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9315
2.5 V and 3.3 V CMOS PLL Clock Generator and Driver
Advanced Clock Drivers Devices
Freescale Semiconductor
Programming the MPC9315
frequencies from 18.75 to 160 MHz. Different feedback and
output divider configurations can be used to achieve the
desired input to output frequency relationship. The feedback
frequency and divider should be used to situate the VCO in
the frequency range between 75 and 160 MHz for stable and
optimal operation. The FSELA, FSELB, FSELC pins select
the desired output clock frequencies. Possible frequency
Table 9. Output Frequency Relationship for QA0 connected to FB0
Table 10. Output Frequency Relationship for QB0 connected to FB0
Table 11. Output Frequency Relationship for QC0 connected to FB0
1. Output frequency relationship with respect to input reference frequency CLK.
1. Output frequency relationship with respect to input reference frequency CLK.
1. Output frequency relationship with respect to input reference frequency CLK.
The PLL of the MPC9315 supports output clock
FSELA
FSELA
FSELA
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FSELB
FSELB
FSELB
Inputs
Inputs
Inputs
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
APPLICATIONS INFORMATION
FSELC
FSELC
FSELC
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
7
ratios of the reference clock input to the outputs are 1:1, 1:2,
1:4 as well as 2:1 and 4:1,
illustrate the various output configurations and frequency
ratios supported by the MPC9315. PSELA controls the output
phase of the QA0 and QA1 outputs, allowing the user to
generate inverted clock signals synchronous to non-inverted
clock signals. See also
MPC9315
QA0, QA1
QA0, QA1
QA0, QA1
CLK ÷ 2
CLK ÷ 2
2 * CLK
2 * CLK
2 * CLK
4 * CLK
2 * CLK
4 * CLK
2 * CLK
2 * CLK
(1)
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
(1)
(1)
for further reference.
Example Configurations for the
QB0–QB3
QB0–QB3
QB0–QB3
Outputs
Outputs
Outputs
CLK ÷ 2
CLK ÷ 2
2 * CLK
2 * CLK
2 * CLK
4 * CLK
2 * CLK
2 * CLK
4 * CLK
2 * CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Table
9,
Table
10, and
QC0, QC1
QC0, QC1
QC0, QC1
CLK ÷ 2
CLK ÷ 4
CLK ÷ 2
CLK ÷ 4
CLK ÷ 2
CLK ÷ 2
CLK ÷ 2
CLK ÷ 4
CLK ÷ 2
CLK ÷ 2
CLK ÷ 4
CLK ÷ 2
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Table 11
MPC9315
NETCOM
MPC9315
7