mpc9315far2 Integrated Device Technology, mpc9315far2 Datasheet - Page 6

• Manufacturer Part Number: mpc9315far2
• Description: 2.5v And 3.3v Lvcmos Pll Clock Generator
• Manufacturer: Integrated Device Technology

IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9315
2.5 V and 3.3 V CMOS PLL Clock Generator and Driver
6
Table 8. AC Characteristics (V
MPC9315
1. AC characteristics apply for parallel output termination of 50 Ω to V
2. ÷1 feedback is responsible for V
3. I/O jitter depends on VCO frequency. Please see application section for I/O jitter versus VCO frequency characteristics.
Symbol
t
t
t
t
JIT(PER)
PLZ, HZ
t
t
PZL, LZ
JIT(CC)
t
f
f
f
SK(∅)
JIT(∅)
refDC
LOCK
t
t
BW
VCO
MAX
t
DC
f
r
r
(∅)
ref
, t
, t
f
f
Input Frequency
VCO Lock Range
Maximum Output Frequency
Reference Input Duty Cycle
CLK0, CLK1 Input Rise/Fall Time
Propagation Delay
(Static Phase Offset)
Output-to-Output Skew
Output Duty Cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
PLL closed loop bandwidth
Cycle-to-Cycle Jitter
Period Jitter
I/O Phase Jitter
Maximum PLL Lock Time
Characteristics
CC
CC
= 2.5 V ± 5%, T
= 2.5 V operation. Please see application section for I/O jitter versus VCO frequency characteristics.
CLK0 or CLK1 to FB
PLL bypass mode
Within one bank
÷2 feedback
÷4 feedback
÷2 feedback
÷4 feedback
Any output
÷1 output
÷2 output
÷4 output
(1σ)
(1σ)
(1σ)
A
= -40° to 85°C)
37.50
18.75
37.50
18.75
75
-150
Min
0.1
75
25
45
0
(2)
TT
6
.
(1)
10 - 25
0.4 - 3.0
1.0 - 10
Typ
8.0
50
10
(3)
160
+150
TBD
TBD
Max
160
120
1.0
1.0
1.0
80
40
80
40
75
80
55
12
12
22
15
(2)
Advanced Clock Drivers Devices
Freescale Semiconductor
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
ns
ps
ps
ps
ns
ns
ns
ps
ps
ps
%
%
PLL locked
PLL locked
VCCA = GND
0.7 to 1.7 V
PLL locked
0.55 to 2.4 V
RMS value
RMS value
RMS value
Condition
NETCOM
MPC9315