mpc9315far2 Integrated Device Technology, mpc9315far2 Datasheet - Page 12

• Manufacturer Part Number: mpc9315far2
• Description: 2.5v And 3.3v Lvcmos Pll Clock Generator
• Manufacturer: Integrated Device Technology

IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9315
2.5 V and 3.3 V CMOS PLL Clock Generator and Driver
MPC9315
12
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
The deviation in t
in a random sample of cycles
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
TCLK0, 1
FB0, 1
Figure 16. Output Duty Cycle (DC)
Figure 18. Cycle-to-Cycle Jitter
0
t
P
for a controlled edge with respect to a t
T
Figure 20. I/O Jitter
N
T
0
T
DC = t
N+1
P
/T
0
T
Figure 15. Propagation delay (t
x 100%
JIT(∅)
CLK0, 1
FB0, 1
T
JIT(CC)
= |T
0
–T
= |T
1
V
GND
mean|
N
CC
–T
N+1
V
CC
0
|
mean
÷ 2
t
(∅)
12
(∅)
, SPO) Test Reference
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles
Figure 21. Output Transition Time Test Reference
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
t
F
Figure 17. Output-to-Output Skew t
T
V
V
GND
V
V
GND
0
CC
CC
CC
CC
Figure 19. Period Jitter
÷ 2
÷ 2
Advanced Clock Drivers Devices
t
SK(O)
Freescale Semiconductor
T
t
R
JIT(PER)
V
CC
0.55
=3.3 V
2.4
= |T
N
–1/f
SK(O)
0
V
|
CC
V
V
GND
V
V
GND
1.8 V
0.6 V
=2.5 V
CC
CC
CC
CC
NETCOM
÷ 2
÷ 2
MPC9315