mpc9315far2 Integrated Device Technology, mpc9315far2 Datasheet - Page 9

• Manufacturer Part Number: mpc9315far2
• Description: 2.5v And 3.3v Lvcmos Pll Clock Generator
• Manufacturer: Integrated Device Technology

IDT™ 2.5 V and 3.3 V CMOS PLL Clock Generator and Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9315
2.5 V and 3.3 V CMOS PLL Clock Generator and Driver
Advanced Clock Drivers Devices
Freescale Semiconductor
Using the MPC9315 in Zero-Delay Applications
for its use as a zero delay buffer. The PLL aligns the feedback
clock output edge with the clock input reference edge and
virtually eliminates the propagation delay through the device.
MPC9315 in zero-delay applications is measured between
the reference clock input and any output. This effective delay
consists of the static phase offset (SPO or t
(t
the output-to-output skew (t
output.
Calculation of Part-to-Part Skew
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs (TCLK or PCLK)
of two or more MPC9315 are connected together, the
maximum overall timing uncertainty from the common TCLK
input to any output is:
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from
Table 12. Confidence Factor CF
TCLK
JIT(∅)
Any Q
The external feedback option of the MPC9315 PLL allows
The remaining insertion delay (skew error) of the
The MPC9315 zero delay buffer supports applications
This maximum timing uncertainty consists of 4
Due to the statistical nature of I/O jitter, an RMS value (1 σ)
± 1σ
± 2σ
± 3σ
± 4σ
± 5σ
± 6σ
QFB
CF
Any Q
Figure 7. MPC9315 max. Device-to-Device Skew
COMMON
t
QFB
Max. skew
SK(PP)
, phase or long-term jitter), feedback path delay and
Device 1
Device 1
Device 2
Device2
Probability of Clock Edge within the Distribution
= t
(∅)
+ t
SK(O)
t
JIT(∅)
Table
—t
+t
+ t
SK(O)
SK(O)
(ý)
PD, LINE(FB)
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
12.
+t
relative to the feedback
(∅)
t
JIT(∅)
t
SK(PP)
+ t
(∅)
t
PD,LINE(FB)
+t
JIT(∅)
SK(O)
), I/O jitter
• CF
9
Figure 9. Max. I/O Jitter (RMS) versus frequency for V
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation, an
I/O jitter confidence factor of 99.7% (± 3σ) is assumed,
resulting in a worst case timing uncertainty from input to any
output of –300 ps to +300 ps relative to TCLK (V
and f
shown in the AC characteristic table for V
RMS). I/O jitter is frequency-dependant with a maximum at
the lowest VCO frequency (160 MHz for the MPC9315).
Applications using a higher VCO frequency exhibit less I/O
jitter than the AC characteristic limit. The I/O jitter
characteristics in
a smaller I/O jitter number at the specific VCO frequency,
resulting in tighter timing limits in zero-delay mode and for
part-to-part skew t
Figure 8. Max. I/O Jitter (RMS) versus frequency for V
The feedback trace delay is determined by the board
t
t
Above equation uses the maximum I/O jitter number
SK(PP)
SK(PP)
30
25
20
15
10
30
25
20
15
10
5
0
VCO
5
0
75
75
I/O Jitter (RMS) versus VCO frequency
= 160 MHz):
= [–150ps...150ps] + [–150ps...150ps] +
= [–300ps...300ps] + t
[(10ps @ –3)...(10ps @ 3)] + t
I/O Jitter (RMS) versus VCO frequency
100
100
Figure 8
SK(PP)
.
125
125
= 3.3 V
and
= 2.5 V
Figure 9
PD, LINE(FB)
150
150
VCO frequency (MHz)
can be used to derive
VCO frequency [MHz]
PD, LINE(FB)
CC
= 3.3 V (10 ps
175
175
CC
MPC9315
= 3.3 V
200
200
NETCOM
CC
CC
MPC9315
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