bbt3821 Intersil Corporation, bbt3821 Datasheet - Page 49

• Manufacturer Part Number: bbt3821
• Description: Octal Multi-rate Lx4/cx4 - Xaui Re-timer
• Manufacturer: Intersil Corporation

Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (2): These bits are overridden by PHY XS XAUI_EN, see also Table 65.
Note (3): This state machine is implemented according toIEEE 802.3ae-2002 clause 48.
Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (2): These bits are overridden to FE’h by PHY XS XAUI_EN, see Table 65 and Table 81.
Note (1): The default value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (1): Loopback is from XAUI Serial I/P to Serial O/P. Recommended use for test purposes only; no retiming or pre-emphasis is performed
Note (2): These values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
4.49153.2:0
4.49154.15:8
4.49154.7:0
4.49155.15:8
4.49155.7:0
4.49156.15:13
4.49156.12
4.49156.11
4.49156.10
4.49156.9
4.49156.8
4.49156.7:4
4.49156.3
4.49156.2
4.49156.1
4.49156.0
BIT
BIT
BIT
BIT
MF_CTRL
Reserved
PHY XS
ERROR
Reserved
PHY XS
XG_IDLE
Reserved
Test LP
SLP_3
SLP_2
SLP_1
SLP_0
Reserved
PLP_3
PLP_2
PLP_1
PLP_0
NAME
NAME
NAME
NAME
49
Table 84. PHY XS MISCELLANEOUS LOOP BACK CONTROL REGISTER
Desired Value
1 = enable
1 = enable PHY XS
Network Loopback
0 = disable
1 = enable System (“PCS”)
Parallel Loopback
0 = disable
0 = BIST_ERR
1 = LOS
2,3 = Reserved
4 = TXFIFO_ERR
5 = AFIFO_ERR
6 = EFIFO_ERR
Desired Value
Table 82. PHY XS INTERNAL ERROR CODE REGISTER
Table 81. PHY XS CONTROL REGISTER 3 (Continued)
Table 83. PHY XS INTERNAL IDLE CODE REGISTER
MDIO REGISTER, ADDRESS = 4.49154 (4.C002’h)
MDIO REGISTER ADDRESS = 4.49153 (4.C001’h)
MDIO REGISTER ADDRESS = 4.49155 (4.C003’h)
MDIO REGISTER ADDRESS = 4.49156 (4.C004’h)
SETTING
SETTING
SETTING
SETTING
(2)
BBT3821
FE’h
07’h
DEFAULT
000’b
DEFAULT
DEFAULT
0’b
0’b
0’b
0’b
0’b
0’b
0’b
0’b
0’b
DEFAULT
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Control the meaning of Multi-function pins MF[3:0] of
the 4 lanes in the device selected by MF_SEL above
(bit 12)
Error Code. These bits allow the internal FIFO
ERROR control character to be programmed.
IDLE pattern in internal FIFOs for translation
to/from XAUI IDLEs
Serial Host Test Loopback
Internal PHY XS Serial Loop Back Enable for each
individual lane. When high, it routes the internal
XAUI Serial output to the Serial input.
PCS Parallel Loop Back Enable for each individual
lane. When high, it routes the XAUI Serial input to
the Serial output via the full PHY XS.
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION